VHDL CODE

(Structured Logic Device Description)

Below is the final VHDL code we used to program the CPLD with. Stiff penalties will result for anyone that thinks they can use the following code for their own plagiaristic purposes and get away with it!  

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;         -- necessary libraries
use IEEE.std_logic_arith.all;

entity triac2 is

    port (zcd, mode, fastclock : in std_logic; 
    duty_cycle : in std_logic_vector (3 downto 0);      -- input / output declarations
    trigger : out std_logic);

end triac2;

architecture t_a of triac2 is

    signal trigger1, trigger2 : std_logic;
    signal state : std_logic_vector (3 downto 0);                 -- signal declaration
    signal state2 : std_logic_vector (3 downto 0);

begin

    process(fastclock)                         -- first process (for delayed trigger mode)
                                                         -- fast clock is an external clock input that
    begin                                             -- runs 16 times as fast as zcd

        if fastclock'EVENT and fastclock = '1' then

            if mode = '0' then -- delayed trigger mode 

                state2 <= state2 + "0001";                                         -- increment state

                    if duty_cycle = "1111" then 
                        trigger1 <= '1';
                    elsif state2 <= ("1111" - duty_cycle) then
                        trigger1 <= '0';
                    else                                                     -- delay for length of (1 - duty cycle)
                        trigger1 <= '1';                                -- and then set trigger1 = 1 for the duty 
                    end if;                                                 -- cycle

            end if;

       end if;

    end process;

    process(zcd)                                     -- second process (for burst mode)

    begin

        if zcd'EVENT and zcd = '1' then 

            if mode = '1' then                                 -- burst mode 

                state <= state + "0001";                     -- increment state

                    if duty_cycle = "0000" then 
                        trigger2 <= '0';
                    elsif state <= duty_cycle then                     -- Set trigger2 = 1 at start and 
                        trigger2 <= '1';                                      -- leave on for length of duty cycle.
                    else                                                           -- Then, set trigger2 = 0 for rest of
                        trigger2 <= '0';                                      -- cycle. 
                    end if;

           end if;

        end if;

    end process;

    trigger <= (trigger1 and not mode) or (trigger2 and mode);                 -- output trigger 

end t_a;