The Progress Story

We certainly came a very long way in terms of progress when gauged against the work we submitted for Phase 1.  Essentially, we developed a much better understanding of what was required from us.  We acquired a thorough understanding of precisely how the Triac works in both Burst Mode and Delayed Trigger Mode.  In addition, we were finally able to produce a VHDL code that worked the way we wanted it to.  

It certainly took us a while to grasp the concepts of both burst mode and delayed trigger mode.  In fact, until recently, we were unaware that delayed trigger mode was actually a sub case of burst mode, and we had to rethink a major portion of our VHDL code in order to introduce an external clock that would run 16x faster than the normal clock.

Initially, we figured we had to build two separate circuits (one for burst mode using a binary counter and a digital magnitude comparator and one for delayed trigger mode using a one shot) and then use the CPLD and debugger board to select which one to use at any given moment.  This approach was much like the Memory Lab, but was not what was intended.

We later learned that VHDL code and the CPLD could satisfy all our needs.  Our original code consisted mainly of if statements, loops, and an integer counter which wouldn't fit on the chip.  Basically, we were looking at the problem from a 'C' language point of view.  Then, we began to think in terms of a state machine with 16 different states, but couldn't properly implement delayed trigger mode with code only.  Finally, we were able to get our code to work with an external clock running 16x faster than the normal one, and shortly after, success was achieved.  

One of the major problems occurred in delayed trigger mode, and it involved the external clock.  We found it incredibly difficult to slow down the 'fast clock' pulse to a halt, and match up it's rising edge with the rising edge of the output trigger.  Achieving this involved working around with the dial on the wave generator in order to arrive at a frequency that would cause the output lamp to stop blinking, and have the waveforms of the input and output match up.  We could never get the waveform to slow down completely, but were able to demonstrate delayed trigger mode effectively when the waveform was in the region we wanted it to be in, which was good enough for our purposes.