library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY stepper4 IS

	PORT
	(
		clock_240hz				: IN		STD_LOGIC;
		ADC_in					: IN		STD_LOGIC_VECTOR(7 DOWNTO 0);
		clock_120hz				: BUFFER	STD_LOGIC;
		clock_60Hz  			: BUFFER    STD_LOGIC;
		clock_out				: OUT   	STD_LOGIC;
		mode_out				: OUT		STD_LOGIC);
END stepper4;

ARCHITECTURE a OF stepper4 IS

	SIGNAL	count_120hz: STD_LOGIC_VECTOR(4 DOWNTO 0);
	SIGNAL	count_60hz: STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL  clock_120hz_int, clock_60hz_int: STD_LOGIC;
BEGIN
	PROCESS
	BEGIN
-- Divide by 2
		WAIT UNTIL clock_240hz'EVENT and clock_240hz = '1';
			IF count_120hz < 3 THEN
				count_120hz <= count_120hz + 1;
			ELSE
				count_120hz <= "00000";
			END IF;
			IF count_120hz < 2 THEN
				clock_120hz_int <= '0';
			ELSE
				clock_120hz_int <= '1';
			END IF;
			clock_120Hz <= clock_120Hz_int;
		END PROCESS;
PROCESS
	BEGIN
-- Divide by 4
		WAIT UNTIL clock_240hz'EVENT and clock_240hz = '1';
			IF count_60hz < 4 THEN
				count_60hz <= count_60hz + 1;
			ELSE
				count_60hz <= "000";
			END IF;
			IF count_60hz < 1 THEN
				clock_60hz_int <= '0';
			ELSE
				clock_60hz_int <= '1';
			END IF;
			clock_60Hz <= clock_60Hz_int;
		END PROCESS;
PROCESS(ADC_in)
  BEGIN
      IF ((ADC_in > "01000100") and (ADC_in < "01011010")) then
        clock_out <= '0';
      ELSIF (ADC_in <= "00001111") then
        mode_out <= '1';
        clock_out <= clock_240hz;
      ELSIF (ADC_in = "01000100") then
        mode_out <= '1';
        clock_out <= clock_60hz;
      ELSIF (ADC_in < "01000100") then
        mode_out <= '1';
        clock_out <= clock_120hz;
      ELSIF (ADC_in >= "11010111") then
        mode_out <= '0';
        clock_out <= clock_240hz;
      ELSIF (ADC_in = "01011010") then
        mode_out <= '0';
        clock_out <= clock_60hz;
      ELSIF (ADC_in > "01011010") then
        mode_out <= '0';
        clock_out <= clock_120hz;
      END IF;
END PROCESS;
END a;