library IEEE; use IEEE.std_logic_1164.all; entity password_get is port( clk : in std_logic; key_inp : in std_logic_vector(1 downto 0); --input (password) from keypad clear : in std_logic; pass_out : out std_logic_vector(7 downto 0) ); end password_get; architecture behaviour of password_get is signal pass_reg : std_logic_vector(7 downto 0); signal got_input : std_logic_vector(2 downto 0); --000 no input --001 first character --010 second character --011 third character --100 fourth char signal obtain : std_logic; signal reset : std_logic; begin process(clk) begin if clk'EVENT and clk='1' then if got_input ="000" or got_input ="001" or got_input ="010" or got_input ="011" or got_input ="100" then reset<='0'; else reset<='1'; end if; if reset='1' or clear='1' then got_input <= "000"; pass_reg<="00000000"; obtain<='0'; reset<='0'; --get first char elsif key_inp /= "00" and got_input="000" and obtain='0' then got_input<="001"; pass_reg(1 downto 0)<=key_inp; obtain<='1'; --get sencond char elsif key_inp/="00" and got_input="001" and obtain='0' then got_input<="010"; pass_reg(3 downto 2)<=key_inp; obtain<='1'; --get third char elsif key_inp/="00" and got_input="010" and obtain='0' then got_input<="011"; pass_reg(5 downto 4)<=key_inp; obtain<='1'; --get fourth char elsif key_inp/="00" and got_input="011" and obtain='0' then got_input<="100"; pass_reg(7 downto 6)<=key_inp; obtain<='1'; --go back to initial state elsif key_inp="00" and got_input="100" then got_input<="000"; end if; if key_inp="00" then obtain<='0'; end if; pass_out<=pass_reg; end if; end process; end behaviour; library IEEE; use IEEE.std_logic_1164.all; package password_get_package is component password_get port( clk : in std_logic; key_inp : in std_logic_vector(1 downto 0); --input (password) from keypad clear : in std_logic; pass_out : out std_logic_vector(7 downto 0) ); end component; end password_get_package;