LIBRARY ieee;					
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;


entity delay is
	port(
			clk				:	in	std_logic;
			start_delay		:	in	std_logic;	--input signal to start delay count
			reset			:	in	std_logic;	--signal in to reset the delay_done signal (go back to idle state)
			delay_done		:	out	std_logic	--0 when delay not done or in idle state, 1 when delay finished
		);
end delay;


architecture behaviour of delay is

signal delay_state	: std_logic_vector(1 downto 0);
--00	idle state
--01	counting state
--10	done counting state(delay_done goes high)

begin
process	(clk)
variable cnt	:	integer range 0 to 900;
		begin
		if clk'EVENT and clk='1' then
			
			--reset
			if reset='1' and (delay_state="10" or delay_state="01") then
				delay_done<='0';
				delay_state<="00";
				cnt:=0;

			--go to counting state			
			elsif delay_state="00" and start_delay='1' then
				delay_state<="01";
				
			--go to done count state
			elsif 	delay_state="01" and cnt >= 10 then
				delay_state<="10";
				delay_done<='1';

			--increment the count
			elsif delay_state="01" then
				cnt:=cnt + 1;
			end if;

		end if; --clock
end process;
end behaviour;

--delay package
library IEEE;
use IEEE.std_logic_1164.all;

package delay_package is
	component delay
	port(
			clk				:	in	std_logic;
			start_delay		:	in	std_logic;	--input signal to start delay count
			reset			:	in	std_logic;	--singnal in to reset the delay_done signal (go back to idle state)
			delay_done		:	out	std_logic	--0 when delay not done or in idle state, 1 when delay finished
		);
	end component;
end delay_package;