library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

package sevenseg_package is
	component sevenseg
		port(A : in std_logic_vector (2 downto 0);
		 BI_L: in std_logic;
		 sega, segb, segc,segd,sege,segf,segg : out std_logic);
end component;
end sevenseg_package;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sevenseg is
	port(A : in std_logic_vector (2 downto 0);
		 BI_L: in std_logic;
		 sega, segb, segc,segd,sege,segf,segg : out std_logic);
end sevenseg;

architecture segma of sevenseg is
		
begin	
	process (BI_L)
	begin
		if BI_L' EVENT and BI_L = '0' then			
			CASE A IS

					when "000" =>					
						
						sega <= '1';
						segb <= '1';
						segc <= '1';
						segd <= '1';
						sege <= '1';
						segf <= '1';
						segg <= '0';

					when "001" =>
						
						sega <= '0';
						segb <= '1';
						segc <= '1';
						segd <= '0';
						sege <= '0';
						segf <= '0';
						segg <= '0';
					when "010" =>
						sega <= '1';
						segb <= '1';
						segc <= '0';
						segd <= '1';
						sege <= '1';
						segf <= '0';
						segg <= '1';
					when "011" =>
						sega <= '1';
						segb <= '1';
						segc <= '1';
						segd <= '1';
						sege <= '0';
						segf <= '0';
						segg <= '1';
					when "100" =>
						sega <= '0';
						segb <= '1';
						segc <= '1';
						segd <= '0';
						sege <= '0';
						segf <= '1';
						segg <= '1';
					when "101" =>
						sega <= '1';
						segb <= '0';
						segc <= '1';
						segd <= '1';
						sege <= '0';
						segf <= '1';
						segg <= '1';
							
					when "110" =>
						sega <= '1';
						segb <= '0';
						segc <= '1';
						segd <= '1';
						sege <= '1';
						segf <= '1';
						segg <= '1';
					when "111" =>						
						sega <= '1';
						segb <= '1';
						segc <= '1';
						segd <= '0';
						sege <= '0';
						segf <= '0';
						segg <= '0';					
					when others => null;
		end case;
end if;
end process;
end segma;