library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;


ENTITY speedstep IS

	PORT
	(
		FASTER				: IN	STD_LOGIC;
		SLOWER				: IN	STD_LOGIC;

		clk					: IN	STD_LOGIC;

		twenty_1			: IN	STD_LOGIC;
		fourty_1			: IN	STD_LOGIC;
		eighty_1			: IN	STD_LOGIC;
		onesixty_1			: IN	STD_LOGIC;
		twenty_2			: IN	STD_LOGIC;
		fourty_2			: IN	STD_LOGIC;
		eighty_2			: IN	STD_LOGIC;
		onesixty_2			: IN	STD_LOGIC;

		fast_1				: OUT	STD_LOGIC;
		slow_1				: OUT	STD_LOGIC;
		fast_2				: OUT	STD_LOGIC;
		slow_2				: OUT	STD_LOGIC);


END speedstep;

ARCHITECTURE a OF speedstep IS
	
	SIGNAL	gear : STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN


	PROCESS
	BEGIN

	WAIT UNTIL clk'EVENT and clk = '1';
		IF FASTER = '1' and SLOWER = '0' THEN		
			IF gear = "000" THEN
				gear <= "100";
			ELSIF gear = "100" THEN
				gear <= "010";
			END IF;
		ELSIF FASTER = '0' and SLOWER = '1' THEN
			IF gear = "100" THEN
				gear <= "000";
			ELSIF gear = "010" THEN
				gear <= "100";
			END IF;
		END IF;


	END PROCESS;


--	PROCESS
--	BEGIN

--		WAIT UNTIL SLOWER'EVENT and SLOWER = '1';
--			gear <= gear;
--			IF gear = "100" THEN
--				gear <= "000";
--			ELSIF gear = "010" THEN
--				gear <= "100";
--			END IF;

--	END PROCESS;


	PROCESS
	BEGIN
		IF gear = "000" THEN
			fast_1 <= eighty_1;
			slow_1 <= onesixty_1;
			fast_2 <= eighty_2;
			slow_2 <= onesixty_2;
		ELSIF gear = "100" THEN
			fast_1 <= fourty_1;
			slow_1 <= eighty_1;
			fast_2 <= fourty_2;
			slow_2 <= eighty_2;
		ELSIF gear = "010" THEN
			fast_1 <= twenty_1;
			slow_1 <= fourty_1;
			fast_2 <= twenty_2;
			slow_2 <= fourty_2;
		END IF;
	END PROCESS;

END a;