LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.all;
USE  IEEE.STD_LOGIC_ARITH.all;
USE  IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY db2clk IS

	PORT
	(
		clock_25Mhz				: IN	STD_LOGIC;
		clock_1Khz				: OUT	STD_LOGIC;
		clock_500hz 			: OUT	STD_LOGIC);
			
END db2clk;

ARCHITECTURE a OF db2clk IS

	SIGNAL	count_500hz: STD_LOGIC_VECTOR(15 DOWNTO 0);
    SIGNAL  count_1Khz: STD_LOGIC_VECTOR(14 DOWNTO 0); 
	SIGNAL  clock_500hz_int, clock_1Khz_int: STD_LOGIC; 
	
BEGIN
	PROCESS 
	BEGIN
-- 1000 Hz
		WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
			IF count_1Khz < 24999 THEN
				count_1Khz <= count_1Khz + 1;
			ELSE
				count_1Khz <= "000000000000000";
			END IF;
			IF count_1Khz < 12499 THEN
				clock_1Khz_int <= '0';
			ELSE
				clock_1Khz_int <= '1';
			END IF;	

		-- Ripple clocks are used in this code to save prescalar hardware
		-- Sync all clock prescalar outputs back to master clock signal
			clock_1Khz <= clock_1Khz_int;
			clock_500hz <= clock_500hz_int;
			
	END PROCESS;	
	PROCESS 
	BEGIN
		WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
			IF count_500hz < 49999 THEN
				count_500hz <= count_500hz + 1;
			ELSE
				count_500hz <= "0000000000000000";
			END IF;
			IF count_500hz < 24999 THEN
				clock_500hz_int <= '0';
			ELSE
				clock_500hz_int <= '1';
			END IF;	

	END PROCESS;	
END a;































































































































































































-- Dave & Bryan