library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

PACKAGE set_time_package IS
	COMPONENT set_time
		port(
		reset, clk	: in std_logic;
		timeb, minb, hrb	: in std_logic;
		min	: out std_logic_vector(5 downto 0);
		hr	: out std_logic_vector(4 downto 0)
		);

	END COMPONENT;

END set_time_package;


-- increment time
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


-- reset is to initialize the set_time
-- timeb is use to increment (synchronous)
-- min: the minute
-- hr: the hour

entity set_time is
	port(
		reset,  clk	: in std_logic;
		timeb, minb, hrb : in std_logic;
		min	: out std_logic_vector(5 downto 0);
		hr	: out std_logic_vector(4 downto 0)
		);
end set_time;

architecture behaviour of set_time is


type state_type is (idle, settime);
signal state: state_type;
signal next_state	:state_type;

begin

mode		:process(state)
	
	begin
	   case state is
	   	when idle => next_state <= settime;	     
	   	when others => NULL;
	   end case;
	 
	 end process mode;  
	   
	   
n_state	:process(clk,reset)	
	begin
		if clk'EVENT and clk='1'then
			if reset = '1' then
				state <= idle;
			elsif reset = '0' then
				state <= next_state;
			end if;
		end if;
	end process n_state;	   

change		:process(timeb,  state,clk)
	variable m1,m2: std_logic_vector(5 downto 0);
	variable h1,h2: std_logic_vector(4 downto 0);
	begin
	if clk'EVENT and clk='1' then
	  case state is
	  	when idle =>
			m1 := "000000";	
			h1 := "00000";
			m2 := "000000";	
			h2 := "00000";
		when settime =>
		  if timeb = '1' then 	
		   	if minb = '1' then
			  if m1 /= "111011" then
				m2 := m1+'1';
				m1 := m2;
			  else
				m1 := "000000";
				m2 := "000000";
			  end if;

		   	elsif hrb = '1' then
			  if h1 /= "10111" then
				h2 := h1+'1';
				h1 := h2;
			  else
				h1 := "00000";
				h2 := "00000";
			  end if;

		   	end if;
		   end if;
		 when others => NULL;
	  end case; 
	  min <= m1;
	  hr <= h1;
	end if;
end process change;
end behaviour;

