library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
--use ieee.std_logic_arith.all;

ENTITY conv IS
	
	PORT(
		clk : in std_logic;
		min_in	: in std_logic_vector(4 downto 0);
		hr_in	: in std_logic_vector(4 downto 0);
		--dismao : out std_logic_vector(3 downto 0);
		--dismbo : out std_logic_vector(3 downto 0);		
		--dishao : out std_logic_vector(3 downto 0);
		--dishbo : out std_logic_vector(3 downto 0)
        hourout : out integer
		);
	END conv;

ARCHITECTURE a OF conv IS
	--signal mina, minb, houra, hourb : integer;
 	signal hour, min : integer;
	--signal disma : std_logic_vector(3 downto 0);
	--signal dismb : std_logic_vector(3 downto 0);		
	--signal disha : std_logic_vector(3 downto 0);
	--signal dishb : std_logic_vector(3 downto 0);


BEGIN
	
    process (clk, min_in, hr_in)
	--type min is range 0 to 250;-- integer;

	begin
	 if clk'event and clk ='1' then
		--min <= conv_integer(min_in);
  		hourout <= conv_integer(hr_in);

end if;
end process;
END a;