PC/CP120 Digital Electronics Lab

Quartus II - Functional and Timing Simulation

In this tutorial, we will show the difference between functional simulation and timing simulation.

Background

There are two different reasons to simulate a digital circuit:

1. To see that your logic is correct
2. To see the effects of propagation delay in the circuit

It should be obvious that if your logic is wrong, there's not much point in looking at the delays.
In order to check the logic of your circuit, you want to do a functional simulation. In this case, all of the delays are assumed to be zero.

Performing a Functional Simulation

To perform a functional simulation, choose the Simulator Tool from the "Processing" menu.

Choose "Functional" as the simulation mode.
Then you must click the button to "Generate Functional Simulation Netlist".
When this completes, you can choose to Start the simulation.
After the simulation completes successfully, you can click the Report button to see the output.
Looking at the report, you should see that all outputs change at exactly the same time as the inputs, reflecting the fact that all delays were assumed to be zero.

Performing a Timing Simulation

To perform a timing simulation, choose the Simulator Tool from the "Processing" menu, and choose "Timing" as the simulation mode.

(Notice that now the "Generate Functional Simulation Netlist" button is greyed out.)
Click Start to begin the simulation.
After the simulation completes successfully, you can click the Report button to see the output.
Looking at the report, you should now that the outputs change some time after the inputs, reflecting the fact that all delays are not actually zero.
You may even see some glitches, where the output changes from one state to the other and back again very quickly when two inputs change at the same time. This is because the delays between each of the inputs and the output are not identical, and so there is a brief period where the effect of one change has occurred but the change of the other hasn't.