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November 22, 2016
This CPLD has a lot more I/O pins than the EMP7064. This allows much
more complex circuits to be programed into it.
Note that there are about 80 I/O pins on the device.
One of the other things about this chip is that is is based on 3.3V
logic, not 5V logic.
This means that you will only use a 3.3V power supply, rather than a 5V power supply so that the chip doesn't get damaged by overvoltage.
The JTAG connector is polarized, so that it can only be
connected the correct way. (Note the notch in the JTAG connector, which
corresponds with the ridge on the JTAG cable from the USB-Blaster.)
Each of these boards has an on-board voltage regulator, so they can be powered with a 9V adapter or battery.
Notice that the I/O pins are in banks. If you look at a bank,
though, you should note that the pins are not always in numerical order.
Because of this, when connecting inputs and outputs it will make sense
to assign pins in the order they appear on the banks, so that
to use ribbon cables to connect to the outside world.
Note that the order of pins will be different on each of these boards.
The idea is that if you are connecting to an external device, (or devices), then if you order the pins in the CPLD to match the order on the external device(s), then your cables simply need to connect 1:1.
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