PC/CP220 Digital Electronics Lab

Other CPLD Boards

Objective:

• Introduce other types of CPLD boards
• Highlight ways to make good use of CPLDs

Background:

These are 3 CPLD boards all based around the same CPLD, the EPM240, which is part of Altera's MAXII family.







The device used is the EPM240T100C5N, from the MAXII family.

What is special about this CPLD?

I/O pins

This CPLD has a lot more I/O pins than the EMP7064. This allows much more complex circuits to be programed into it.



Note that there are about 80 I/O pins on the device.

3.3V logic

One of the other things about this chip is that is is based on 3.3V logic, not 5V logic.
This means that you will only use a 3.3V power supply, rather than a 5V power supply so that the chip doesn't get damaged by overvoltage.

JTAG connector

The JTAG connector is polarized, so that it can only be connected the correct way. (Note the notch in the JTAG connector, which corresponds with the ridge on the JTAG cable from the USB-Blaster.)
Each of these boards has an on-board voltage regulator, so they can be powered with a 9V adapter or battery.

Using pins wisely

Notice that the I/O pins are in banks. If you look at a bank, though, you should note that the pins are not always in numerical order. Because of this, when connecting inputs and outputs it will make sense to assign pins in the order they appear on the banks, so that it's easy to use ribbon cables to connect to the outside world.
Note that the order of pins will be different on each of these boards.

The idea is that if you are connecting to an external device, (or devices), then if you order the pins in the CPLD to match the order on the external device(s), then your cables simply need to connect 1:1.

Because the chip uses 3.3V logic, then if you are taking power from the board for external circuitry it should be from the 3.3V supply to avoid damage to any of the CPLD pins.

Connectors on blue board

It has four connector banks, P1, P2, P3, and P4. Each bank has two rows of connectors. Note that the pin numbers on the connectors are not always consecutive, and so you need to be careful when assigning them.

P1 layout is as follows: This connector can be used to get 3.3V to power other devices.


P2 layout is as follows: Note that pins 43 and 44 are not the same as other I/O pins, and so should be avoided.


P3 layout is as follows:


P4 layout is as follows:
 

Debugger Board

Since the CPLD is a 3.3V device, you can't have any 5V devices connected.
This applies to the debugger board.
However, the logic on the debugger board can also operate on 3.3V.
If the debugger board is powered by 3.3V from the CPLD, then there will be no problem.
P1 has pins for 3.3V and GROUND.
Use P1 pins for +3.3V and GROUND to power the debugger board.

 

Incorporating I/O Circuitry

If your circuit only uses part of a CPLD, you may be able to incorporate input and/or output circuitry inside the CPLD.
You could include a keypad encoder.
You could include a 7 segment display decoder.
This is easy because different circuits can be inside a single CPLD.

Notice that the input and output portions do not have to be connected to each other in any way.