Introduction to CPLD

Programmable logic device, or PLD, is a general name for a digital integrated circuit capable of being programmed to provide a variety of different functions.

Why PLD?

It's good for prototyping designs. Only a single chip is required to implement logic designs. It allows us to simplify designs and reduce development times.  Changes in the design can be easily implemented by reprogramming the device. Simple PLDs (such as the one we use in our lab) can realize from 2 to 10 functions of 4 to 16 variables on a single integrated circuit

Using Altera Quartus II with the CPLD board

Step 1: Open your project. File --> Open Project

Step 2: Selecting your Device

Select Assignments --> Device  from the pull-down menu. Select MAX7000S from the "Family" pull-down list.
Select the "Specific device selected" and then choose EPM7064SLC44-10, which is the device we are using in our lab. Select "OK."

select device

Step 3: Assigning Pins

Select Assignments --> Pins  from the pull-down menu.

You will notice that the pins around the edges of the chip have different symbols. The plain round circles with nothing written insied of them are used for input and output.

Select each input and output from the bottom of the screen and drag it on top of the pin you would like to use - make sure you click on the name. (ie. if you want h to be pin 4, click h on the bottom of the screen and drag it on top of the circle under the label 4). Remember, use ONLY the plain round circles!!

When you are finished you can close the window.

pin assignment screen

Step 4: Compile

You will  need to compile your design again to fit your design on the PLD board.

Click on Processing →  Compiler Tool to start compilation. Then click start.

compile

Step 5: Download your circuit to CPLD board

Setting up Programming Hardware in Quartus II Software:

  1. Choose Programmer from the Tools menu. The Programmer window will open.
  2. Click the Hardware Setup... button to open the Hardware Setup window.
    1. The selected programming hardware is identified as Currently Selected Hardware. If it says ByteBlaster[LPT1] mode JTAG you have the correct hardware (skip to step 5).
    2. Programming hardware that is already set up appears in the Available hardware items window.
  3. If the ByteBlaster is not listed in the Available hardware items window click the Add Hardware button to open the Add Hardware window.
    1. Select the appropriate programming cable or programming hardware from the Hardware Type list.
    2. Select the appropriate port and baud rate if necessary.
    3. Click OK.
  4. Select the programming hardware you would like to use by choosing it in the Available hardware items list.
  5. Click Close.
  6. Your programming hardware has been set up.
  7. At the main window, ensure it displays ByteBlaster[LPT1] mode JTAG  (see figure below)

Connect CPLD board to ByteBlaster cable (connected to LPT1 on your PC).

Connect the ground and power (5v) to the CPLD board and turn the power on.

  1. Click Auto Detect, your program should detect the CPLD
  2. Delete the file that shows up.
  3. Click Add File choose 'pof' file
  4. Check Program/Configure
  5. Select Start, you should see the progress indicator increasing slowly (fast means problem).

programmer

Solving the problems:

Problem Solution
Unable to scan device chain.

This is generally a problem with power. Check:

  1. Is the power and ground connected properly and turned on?
  2. Is the red strip on the Byte Blaster cable connected to the proper side of the board.
JTAG error

This is generally a problem with the connection. Try:

  1. Make sure you have the correct deivce selected
    • ensure 7064 (not 7032)
    • ensure SLC (not STC)
  2. Unplugging the Byte Blaster cable and reconnecting.
  3. Try a new Byte Blaster cable.
  4. Try a new Altera Board
License error

This is generally a problem if you haven't done anything with the software recently. The server times out and loses the connection to the licencing file.

  1. Close Quartus and reopen.

 

Step 6: Find the Pin Assignment

To implement the logic in a CPLD we need to know which pins in the CPLD were assigned to the input and output of the logic.

Quartus assigns the device’s pins to inputs and outputs in your design automatically if you do not assign them.

To look them up, in the main window select Processing → Compilation Report → Fitter →  Pin-Out File. This is a detailed report showing where all of the pins on the CPLD have been assigned.

pin out

Step 7: Wire input and output

You can unplug the Byte Blaster cable and turn off the power while you are wiring your circuit. You will not lose your program.

Use the debugger board to wire the input (use the control mode) and the output (use the display mode). You do not have to wire the Vcc and the GND, only your inputs and outputs. (ie. c, h, p & f)

Step 8: Troubleshooting

If you smell smoke turn off the power immediately and DO NOT touch the Altera chip. It gets extremely hot if it is short circuited. Check all your power and grounds, have someone else check your power and grounds - something IS wrong!! Hopefully, your chip will still work. :)

  1. First, double check your simulation to ensure that your Quartus design is correct. If it is not correct then you will not get the correct output no matter how well everything else is connected.
  2. Next, check your device, even if you think it's right... double check. If you need to change it make sure you recompile.
  3. Check your pin assignments and make sure you have not assigned any of your inputs or outputs to reserved pins or specialized pins. Plain circles only (with no writing inside).
  4. Make sure you have power and ground to boards (Altera, debugger, breadboard).
  5. Make sure you have the debugger board set up for input and output correctly.
  6. If there are a few things right and a few things wrong, check your pins to make sure you are in the correct place and use the multimeter to ensure you have a good connection.