PulseWidthPulseIn.ino.elf: file format elf32-avr Disassembly of section .text: 00000000 <__vectors>: 0: 0c 94 58 00 jmp 0xb0 ; 0xb0 <__ctors_end> 4: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 8: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> c: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 10: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 14: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 18: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 1c: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 20: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 24: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 28: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 2c: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 30: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 34: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 38: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 3c: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 40: 0c 94 1d 02 jmp 0x43a ; 0x43a <__vector_16> 44: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 48: 0c 94 eb 01 jmp 0x3d6 ; 0x3d6 <__vector_18> 4c: 0c 94 c5 01 jmp 0x38a ; 0x38a <__vector_19> 50: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 54: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 58: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 5c: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 60: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 64: 0c 94 80 00 jmp 0x100 ; 0x100 <__bad_interrupt> 00000068 <__trampolines_end>: 68: 00 00 nop 6a: 00 00 nop 6c: 25 00 .word 0x0025 ; ???? 6e: 28 00 .word 0x0028 ; ???? 70: 2b 00 .word 0x002b ; ???? 00000072 : 72: 00 00 00 00 24 00 27 00 2a 00 ....$.'.*. 0000007c : 7c: 00 00 00 00 23 00 26 00 29 00 ....#.&.). 00000086 : 86: 04 04 04 04 04 04 04 04 02 02 02 02 02 02 03 03 ................ 96: 03 03 03 03 .... 0000009a : 9a: 01 02 04 08 10 20 40 80 01 02 04 08 10 20 01 02 ..... @...... .. aa: 04 08 10 20 ... 000000ae <__ctors_start>: ae: cc 03 fmulsu r20, r20 000000b0 <__ctors_end>: b0: 11 24 eor r1, r1 b2: 1f be out 0x3f, r1 ; 63 b4: cf ef ldi r28, 0xFF ; 255 b6: d8 e0 ldi r29, 0x08 ; 8 b8: de bf out 0x3e, r29 ; 62 ba: cd bf out 0x3d, r28 ; 61 000000bc <__do_copy_data>: bc: 11 e0 ldi r17, 0x01 ; 1 be: a0 e0 ldi r26, 0x00 ; 0 c0: b1 e0 ldi r27, 0x01 ; 1 c2: e0 e5 ldi r30, 0x50 ; 80 c4: f8 e0 ldi r31, 0x08 ; 8 c6: 02 c0 rjmp .+4 ; 0xcc <__do_copy_data+0x10> c8: 05 90 lpm r0, Z+ ca: 0d 92 st X+, r0 cc: aa 31 cpi r26, 0x1A ; 26 ce: b1 07 cpc r27, r17 d0: d9 f7 brne .-10 ; 0xc8 <__do_copy_data+0xc> 000000d2 <__do_clear_bss>: d2: 21 e0 ldi r18, 0x01 ; 1 d4: aa e1 ldi r26, 0x1A ; 26 d6: b1 e0 ldi r27, 0x01 ; 1 d8: 01 c0 rjmp .+2 ; 0xdc <.do_clear_bss_start> 000000da <.do_clear_bss_loop>: da: 1d 92 st X+, r1 000000dc <.do_clear_bss_start>: dc: a4 3c cpi r26, 0xC4 ; 196 de: b2 07 cpc r27, r18 e0: e1 f7 brne .-8 ; 0xda <.do_clear_bss_loop> 000000e2 <__do_global_ctors>: e2: 10 e0 ldi r17, 0x00 ; 0 e4: c8 e5 ldi r28, 0x58 ; 88 e6: d0 e0 ldi r29, 0x00 ; 0 e8: 04 c0 rjmp .+8 ; 0xf2 <__do_global_ctors+0x10> ea: 21 97 sbiw r28, 0x01 ; 1 ec: fe 01 movw r30, r28 ee: 0e 94 1b 04 call 0x836 ; 0x836 <__tablejump2__> f2: c7 35 cpi r28, 0x57 ; 87 f4: d1 07 cpc r29, r17 f6: c9 f7 brne .-14 ; 0xea <__do_global_ctors+0x8> f8: 0e 94 ac 02 call 0x558 ; 0x558
fc: 0c 94 26 04 jmp 0x84c ; 0x84c <_exit> 00000100 <__bad_interrupt>: 100: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 00000104 <_ZN5Print5writeEPKhj>: // Public Methods ////////////////////////////////////////////////////////////// /* default implementation: may be overridden */ size_t Print::write(const uint8_t *buffer, size_t size) { 104: cf 92 push r12 106: df 92 push r13 108: ef 92 push r14 10a: ff 92 push r15 10c: 0f 93 push r16 10e: 1f 93 push r17 110: cf 93 push r28 112: df 93 push r29 114: 6c 01 movw r12, r24 116: 7a 01 movw r14, r20 118: 8b 01 movw r16, r22 size_t n = 0; 11a: c0 e0 ldi r28, 0x00 ; 0 11c: d0 e0 ldi r29, 0x00 ; 0 while (size--) { 11e: ce 15 cp r28, r14 120: df 05 cpc r29, r15 122: 89 f0 breq .+34 ; 0x146 <_ZN5Print5writeEPKhj+0x42> if (write(*buffer++)) n++; 124: d8 01 movw r26, r16 126: 6d 91 ld r22, X+ 128: 8d 01 movw r16, r26 12a: d6 01 movw r26, r12 12c: ed 91 ld r30, X+ 12e: fc 91 ld r31, X 130: 01 90 ld r0, Z+ 132: f0 81 ld r31, Z 134: e0 2d mov r30, r0 136: c6 01 movw r24, r12 138: 09 95 icall 13a: 89 2b or r24, r25 13c: 11 f4 brne .+4 ; 0x142 <_ZN5Print5writeEPKhj+0x3e> 13e: 7e 01 movw r14, r28 140: 02 c0 rjmp .+4 ; 0x146 <_ZN5Print5writeEPKhj+0x42> 142: 21 96 adiw r28, 0x01 ; 1 144: ec cf rjmp .-40 ; 0x11e <_ZN5Print5writeEPKhj+0x1a> else break; } return n; } 146: c7 01 movw r24, r14 148: df 91 pop r29 14a: cf 91 pop r28 14c: 1f 91 pop r17 14e: 0f 91 pop r16 150: ff 90 pop r15 152: ef 90 pop r14 154: df 90 pop r13 156: cf 90 pop r12 158: 08 95 ret 0000015a <_ZN5Print5flushEv>: size_t println(unsigned long, int = DEC); size_t println(double, int = 2); size_t println(const Printable&); size_t println(void); virtual void flush() { /* Empty implementation for backward compatibility */ } 15a: 08 95 ret 0000015c <_ZN5Print17availableForWriteEv>: return write((const uint8_t *)buffer, size); } // default to zero, meaning "a single write may block" // should be overriden by subclasses with buffering virtual int availableForWrite() { return 0; } 15c: 80 e0 ldi r24, 0x00 ; 0 15e: 90 e0 ldi r25, 0x00 ; 0 160: 08 95 ret 00000162 <_ZN14HardwareSerial17availableForWriteEv>: { #if (SERIAL_TX_BUFFER_SIZE>256) uint8_t oldSREG = SREG; cli(); #endif tx_buffer_index_t head = _tx_buffer_head; 162: fc 01 movw r30, r24 164: 53 8d ldd r21, Z+27 ; 0x1b tx_buffer_index_t tail = _tx_buffer_tail; 166: 44 8d ldd r20, Z+28 ; 0x1c 168: 25 2f mov r18, r21 16a: 30 e0 ldi r19, 0x00 ; 0 16c: 84 2f mov r24, r20 16e: 90 e0 ldi r25, 0x00 ; 0 #if (SERIAL_TX_BUFFER_SIZE>256) SREG = oldSREG; #endif if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail; 170: 82 1b sub r24, r18 172: 93 0b sbc r25, r19 174: 54 17 cp r21, r20 176: 10 f0 brcs .+4 ; 0x17c <_ZN14HardwareSerial17availableForWriteEv+0x1a> 178: cf 96 adiw r24, 0x3f ; 63 17a: 08 95 ret return tail - head - 1; 17c: 01 97 sbiw r24, 0x01 ; 1 } 17e: 08 95 ret 00000180 <_ZN14HardwareSerial4readEv>: return _rx_buffer[_rx_buffer_tail]; } } int HardwareSerial::read(void) { 180: fc 01 movw r30, r24 // if the head isn't ahead of the tail, we don't have any characters if (_rx_buffer_head == _rx_buffer_tail) { 182: 91 8d ldd r25, Z+25 ; 0x19 184: 82 8d ldd r24, Z+26 ; 0x1a 186: 98 17 cp r25, r24 188: 61 f0 breq .+24 ; 0x1a2 <_ZN14HardwareSerial4readEv+0x22> return -1; } else { unsigned char c = _rx_buffer[_rx_buffer_tail]; 18a: 82 8d ldd r24, Z+26 ; 0x1a 18c: df 01 movw r26, r30 18e: a8 0f add r26, r24 190: b1 1d adc r27, r1 192: 5d 96 adiw r26, 0x1d ; 29 194: 8c 91 ld r24, X _rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE; 196: 92 8d ldd r25, Z+26 ; 0x1a 198: 9f 5f subi r25, 0xFF ; 255 19a: 9f 73 andi r25, 0x3F ; 63 19c: 92 8f std Z+26, r25 ; 0x1a return c; 19e: 90 e0 ldi r25, 0x00 ; 0 1a0: 08 95 ret int HardwareSerial::read(void) { // if the head isn't ahead of the tail, we don't have any characters if (_rx_buffer_head == _rx_buffer_tail) { return -1; 1a2: 8f ef ldi r24, 0xFF ; 255 1a4: 9f ef ldi r25, 0xFF ; 255 } else { unsigned char c = _rx_buffer[_rx_buffer_tail]; _rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE; return c; } } 1a6: 08 95 ret 000001a8 <_ZN14HardwareSerial4peekEv>: { return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE; } int HardwareSerial::peek(void) { 1a8: fc 01 movw r30, r24 if (_rx_buffer_head == _rx_buffer_tail) { 1aa: 91 8d ldd r25, Z+25 ; 0x19 1ac: 82 8d ldd r24, Z+26 ; 0x1a 1ae: 98 17 cp r25, r24 1b0: 31 f0 breq .+12 ; 0x1be <_ZN14HardwareSerial4peekEv+0x16> return -1; } else { return _rx_buffer[_rx_buffer_tail]; 1b2: 82 8d ldd r24, Z+26 ; 0x1a 1b4: e8 0f add r30, r24 1b6: f1 1d adc r31, r1 1b8: 85 8d ldd r24, Z+29 ; 0x1d 1ba: 90 e0 ldi r25, 0x00 ; 0 1bc: 08 95 ret } int HardwareSerial::peek(void) { if (_rx_buffer_head == _rx_buffer_tail) { return -1; 1be: 8f ef ldi r24, 0xFF ; 255 1c0: 9f ef ldi r25, 0xFF ; 255 } else { return _rx_buffer[_rx_buffer_tail]; } } 1c2: 08 95 ret 000001c4 <_ZN14HardwareSerial9availableEv>: // clear any received data _rx_buffer_head = _rx_buffer_tail; } int HardwareSerial::available(void) { 1c4: fc 01 movw r30, r24 return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE; 1c6: 91 8d ldd r25, Z+25 ; 0x19 1c8: 22 8d ldd r18, Z+26 ; 0x1a 1ca: 89 2f mov r24, r25 1cc: 90 e0 ldi r25, 0x00 ; 0 1ce: 80 5c subi r24, 0xC0 ; 192 1d0: 9f 4f sbci r25, 0xFF ; 255 1d2: 82 1b sub r24, r18 1d4: 91 09 sbc r25, r1 } 1d6: 8f 73 andi r24, 0x3F ; 63 1d8: 99 27 eor r25, r25 1da: 08 95 ret 000001dc <_Z17Serial0_availablev>: #endif // Function that can be weakly referenced by serialEventRun to prevent // pulling in this file if it's not otherwise used. bool Serial0_available() { return Serial.available(); 1dc: 87 e2 ldi r24, 0x27 ; 39 1de: 91 e0 ldi r25, 0x01 ; 1 1e0: 0e 94 e2 00 call 0x1c4 ; 0x1c4 <_ZN14HardwareSerial9availableEv> 1e4: 21 e0 ldi r18, 0x01 ; 1 1e6: 89 2b or r24, r25 1e8: 09 f4 brne .+2 ; 0x1ec <_Z17Serial0_availablev+0x10> 1ea: 20 e0 ldi r18, 0x00 ; 0 } 1ec: 82 2f mov r24, r18 1ee: 08 95 ret 000001f0 <_ZN14HardwareSerial17_tx_udr_empty_irqEv>: } // Actual interrupt handlers ////////////////////////////////////////////////////////////// void HardwareSerial::_tx_udr_empty_irq(void) { 1f0: fc 01 movw r30, r24 // If interrupts are enabled, there must be more data in the output // buffer. Send the next byte unsigned char c = _tx_buffer[_tx_buffer_tail]; 1f2: 84 8d ldd r24, Z+28 ; 0x1c 1f4: df 01 movw r26, r30 1f6: a8 0f add r26, r24 1f8: b1 1d adc r27, r1 1fa: a3 5a subi r26, 0xA3 ; 163 1fc: bf 4f sbci r27, 0xFF ; 255 1fe: 2c 91 ld r18, X _tx_buffer_tail = (_tx_buffer_tail + 1) % SERIAL_TX_BUFFER_SIZE; 200: 84 8d ldd r24, Z+28 ; 0x1c 202: 90 e0 ldi r25, 0x00 ; 0 204: 01 96 adiw r24, 0x01 ; 1 206: 8f 73 andi r24, 0x3F ; 63 208: 99 27 eor r25, r25 20a: 84 8f std Z+28, r24 ; 0x1c *_udr = c; 20c: a6 89 ldd r26, Z+22 ; 0x16 20e: b7 89 ldd r27, Z+23 ; 0x17 210: 2c 93 st X, r18 // clear the TXC bit -- "can be cleared by writing a one to its bit // location". This makes sure flush() won't return until the bytes // actually got written sbi(*_ucsra, TXC0); 212: a0 89 ldd r26, Z+16 ; 0x10 214: b1 89 ldd r27, Z+17 ; 0x11 216: 8c 91 ld r24, X 218: 80 64 ori r24, 0x40 ; 64 21a: 8c 93 st X, r24 if (_tx_buffer_head == _tx_buffer_tail) { 21c: 93 8d ldd r25, Z+27 ; 0x1b 21e: 84 8d ldd r24, Z+28 ; 0x1c 220: 98 13 cpse r25, r24 222: 06 c0 rjmp .+12 ; 0x230 <_ZN14HardwareSerial17_tx_udr_empty_irqEv+0x40> // Buffer empty, so disable interrupts cbi(*_ucsrb, UDRIE0); 224: 02 88 ldd r0, Z+18 ; 0x12 226: f3 89 ldd r31, Z+19 ; 0x13 228: e0 2d mov r30, r0 22a: 80 81 ld r24, Z 22c: 8f 7d andi r24, 0xDF ; 223 22e: 80 83 st Z, r24 230: 08 95 ret 00000232 <_ZN14HardwareSerial5writeEh>: // If we get here, nothing is queued anymore (DRIE is disabled) and // the hardware finished tranmission (TXC is set). } size_t HardwareSerial::write(uint8_t c) { 232: ef 92 push r14 234: ff 92 push r15 236: 0f 93 push r16 238: 1f 93 push r17 23a: cf 93 push r28 23c: df 93 push r29 23e: ec 01 movw r28, r24 _written = true; 240: 81 e0 ldi r24, 0x01 ; 1 242: 88 8f std Y+24, r24 ; 0x18 // If the buffer and the data register is empty, just write the byte // to the data register and be done. This shortcut helps // significantly improve the effective datarate at high (> // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { 244: 9b 8d ldd r25, Y+27 ; 0x1b 246: 8c 8d ldd r24, Y+28 ; 0x1c 248: 98 13 cpse r25, r24 24a: 05 c0 rjmp .+10 ; 0x256 <_ZN14HardwareSerial5writeEh+0x24> 24c: e8 89 ldd r30, Y+16 ; 0x10 24e: f9 89 ldd r31, Y+17 ; 0x11 250: 80 81 ld r24, Z 252: 85 fd sbrc r24, 5 254: 24 c0 rjmp .+72 ; 0x29e <_ZN14HardwareSerial5writeEh+0x6c> 256: f6 2e mov r15, r22 *_udr = c; sbi(*_ucsra, TXC0); return 1; } tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE; 258: 0b 8d ldd r16, Y+27 ; 0x1b 25a: 10 e0 ldi r17, 0x00 ; 0 25c: 0f 5f subi r16, 0xFF ; 255 25e: 1f 4f sbci r17, 0xFF ; 255 260: 0f 73 andi r16, 0x3F ; 63 262: 11 27 eor r17, r17 264: e0 2e mov r14, r16 // If the output buffer is full, there's nothing for it other than to // wait for the interrupt handler to empty it a bit while (i == _tx_buffer_tail) { 266: 8c 8d ldd r24, Y+28 ; 0x1c 268: e8 12 cpse r14, r24 26a: 0c c0 rjmp .+24 ; 0x284 <_ZN14HardwareSerial5writeEh+0x52> if (bit_is_clear(SREG, SREG_I)) { 26c: 0f b6 in r0, 0x3f ; 63 26e: 07 fc sbrc r0, 7 270: fa cf rjmp .-12 ; 0x266 <_ZN14HardwareSerial5writeEh+0x34> // Interrupts are disabled, so we'll have to poll the data // register empty flag ourselves. If it is set, pretend an // interrupt has happened and call the handler to free up // space for us. if(bit_is_set(*_ucsra, UDRE0)) 272: e8 89 ldd r30, Y+16 ; 0x10 274: f9 89 ldd r31, Y+17 ; 0x11 276: 80 81 ld r24, Z 278: 85 ff sbrs r24, 5 27a: f5 cf rjmp .-22 ; 0x266 <_ZN14HardwareSerial5writeEh+0x34> _tx_udr_empty_irq(); 27c: ce 01 movw r24, r28 27e: 0e 94 f8 00 call 0x1f0 ; 0x1f0 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> 282: f1 cf rjmp .-30 ; 0x266 <_ZN14HardwareSerial5writeEh+0x34> } else { // nop, the interrupt handler will free up space for us } } _tx_buffer[_tx_buffer_head] = c; 284: 8b 8d ldd r24, Y+27 ; 0x1b 286: fe 01 movw r30, r28 288: e8 0f add r30, r24 28a: f1 1d adc r31, r1 28c: e3 5a subi r30, 0xA3 ; 163 28e: ff 4f sbci r31, 0xFF ; 255 290: f0 82 st Z, r15 _tx_buffer_head = i; 292: 0b 8f std Y+27, r16 ; 0x1b sbi(*_ucsrb, UDRIE0); 294: ea 89 ldd r30, Y+18 ; 0x12 296: fb 89 ldd r31, Y+19 ; 0x13 298: 80 81 ld r24, Z 29a: 80 62 ori r24, 0x20 ; 32 29c: 07 c0 rjmp .+14 ; 0x2ac <_ZN14HardwareSerial5writeEh+0x7a> // If the buffer and the data register is empty, just write the byte // to the data register and be done. This shortcut helps // significantly improve the effective datarate at high (> // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { *_udr = c; 29e: ee 89 ldd r30, Y+22 ; 0x16 2a0: ff 89 ldd r31, Y+23 ; 0x17 2a2: 60 83 st Z, r22 sbi(*_ucsra, TXC0); 2a4: e8 89 ldd r30, Y+16 ; 0x10 2a6: f9 89 ldd r31, Y+17 ; 0x11 2a8: 80 81 ld r24, Z 2aa: 80 64 ori r24, 0x40 ; 64 2ac: 80 83 st Z, r24 _tx_buffer_head = i; sbi(*_ucsrb, UDRIE0); return 1; } 2ae: 81 e0 ldi r24, 0x01 ; 1 2b0: 90 e0 ldi r25, 0x00 ; 0 2b2: df 91 pop r29 2b4: cf 91 pop r28 2b6: 1f 91 pop r17 2b8: 0f 91 pop r16 2ba: ff 90 pop r15 2bc: ef 90 pop r14 2be: 08 95 ret 000002c0 <_ZN14HardwareSerial5flushEv>: if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail; return tail - head - 1; } void HardwareSerial::flush() { 2c0: cf 93 push r28 2c2: df 93 push r29 2c4: ec 01 movw r28, r24 // If we have never written a byte, no need to flush. This special // case is needed since there is no way to force the TXC (transmit // complete) bit to 1 during initialization if (!_written) 2c6: 88 8d ldd r24, Y+24 ; 0x18 2c8: 88 23 and r24, r24 2ca: c9 f0 breq .+50 ; 0x2fe <_ZN14HardwareSerial5flushEv+0x3e> return; while (bit_is_set(*_ucsrb, UDRIE0) || bit_is_clear(*_ucsra, TXC0)) { 2cc: ea 89 ldd r30, Y+18 ; 0x12 2ce: fb 89 ldd r31, Y+19 ; 0x13 2d0: 80 81 ld r24, Z 2d2: 85 fd sbrc r24, 5 2d4: 05 c0 rjmp .+10 ; 0x2e0 <_ZN14HardwareSerial5flushEv+0x20> 2d6: a8 89 ldd r26, Y+16 ; 0x10 2d8: b9 89 ldd r27, Y+17 ; 0x11 2da: 8c 91 ld r24, X 2dc: 86 fd sbrc r24, 6 2de: 0f c0 rjmp .+30 ; 0x2fe <_ZN14HardwareSerial5flushEv+0x3e> if (bit_is_clear(SREG, SREG_I) && bit_is_set(*_ucsrb, UDRIE0)) 2e0: 0f b6 in r0, 0x3f ; 63 2e2: 07 fc sbrc r0, 7 2e4: f5 cf rjmp .-22 ; 0x2d0 <_ZN14HardwareSerial5flushEv+0x10> 2e6: 80 81 ld r24, Z 2e8: 85 ff sbrs r24, 5 2ea: f2 cf rjmp .-28 ; 0x2d0 <_ZN14HardwareSerial5flushEv+0x10> // Interrupts are globally disabled, but the DR empty // interrupt should be enabled, so poll the DR empty flag to // prevent deadlock if (bit_is_set(*_ucsra, UDRE0)) 2ec: a8 89 ldd r26, Y+16 ; 0x10 2ee: b9 89 ldd r27, Y+17 ; 0x11 2f0: 8c 91 ld r24, X 2f2: 85 ff sbrs r24, 5 2f4: ed cf rjmp .-38 ; 0x2d0 <_ZN14HardwareSerial5flushEv+0x10> _tx_udr_empty_irq(); 2f6: ce 01 movw r24, r28 2f8: 0e 94 f8 00 call 0x1f0 ; 0x1f0 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> 2fc: e7 cf rjmp .-50 ; 0x2cc <_ZN14HardwareSerial5flushEv+0xc> } // If we get here, nothing is queued anymore (DRIE is disabled) and // the hardware finished tranmission (TXC is set). } 2fe: df 91 pop r29 300: cf 91 pop r28 302: 08 95 ret 00000304 <_Z14serialEventRunv>: #endif void serialEventRun(void) { #if defined(HAVE_HWSERIAL0) if (Serial0_available && serialEvent && Serial0_available()) serialEvent(); 304: 80 e0 ldi r24, 0x00 ; 0 306: 90 e0 ldi r25, 0x00 ; 0 308: 89 2b or r24, r25 30a: 29 f0 breq .+10 ; 0x316 <_Z14serialEventRunv+0x12> 30c: 0e 94 ee 00 call 0x1dc ; 0x1dc <_Z17Serial0_availablev> 310: 81 11 cpse r24, r1 312: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 316: 08 95 ret 00000318 : return m; } unsigned long micros() { unsigned long m; uint8_t oldSREG = SREG, t; 318: 3f b7 in r19, 0x3f ; 63 cli(); 31a: f8 94 cli m = timer0_overflow_count; 31c: 80 91 1f 01 lds r24, 0x011F 320: 90 91 20 01 lds r25, 0x0120 324: a0 91 21 01 lds r26, 0x0121 328: b0 91 22 01 lds r27, 0x0122 #if defined(TCNT0) t = TCNT0; 32c: 26 b5 in r18, 0x26 ; 38 #else #error TIMER 0 not defined #endif #ifdef TIFR0 if ((TIFR0 & _BV(TOV0)) && (t < 255)) 32e: a8 9b sbis 0x15, 0 ; 21 330: 05 c0 rjmp .+10 ; 0x33c 332: 2f 3f cpi r18, 0xFF ; 255 334: 19 f0 breq .+6 ; 0x33c m++; 336: 01 96 adiw r24, 0x01 ; 1 338: a1 1d adc r26, r1 33a: b1 1d adc r27, r1 #else if ((TIFR & _BV(TOV0)) && (t < 255)) m++; #endif SREG = oldSREG; 33c: 3f bf out 0x3f, r19 ; 63 return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond()); 33e: ba 2f mov r27, r26 340: a9 2f mov r26, r25 342: 98 2f mov r25, r24 344: 88 27 eor r24, r24 346: 82 0f add r24, r18 348: 91 1d adc r25, r1 34a: a1 1d adc r26, r1 34c: b1 1d adc r27, r1 34e: bc 01 movw r22, r24 350: cd 01 movw r24, r26 352: 42 e0 ldi r20, 0x02 ; 2 354: 66 0f add r22, r22 356: 77 1f adc r23, r23 358: 88 1f adc r24, r24 35a: 99 1f adc r25, r25 35c: 4a 95 dec r20 35e: d1 f7 brne .-12 ; 0x354 } 360: 08 95 ret 00000362 <_ZN5Print5writeEPKc.constprop.10>: int getWriteError() { return write_error; } void clearWriteError() { setWriteError(0); } virtual size_t write(uint8_t) = 0; size_t write(const char *str) { if (str == NULL) return 0; 362: 00 97 sbiw r24, 0x00 ; 0 364: 69 f0 breq .+26 ; 0x380 <_ZN5Print5writeEPKc.constprop.10+0x1e> return write((const uint8_t *)str, strlen(str)); 366: fc 01 movw r30, r24 368: 01 90 ld r0, Z+ 36a: 00 20 and r0, r0 36c: e9 f7 brne .-6 ; 0x368 <_ZN5Print5writeEPKc.constprop.10+0x6> 36e: 31 97 sbiw r30, 0x01 ; 1 370: af 01 movw r20, r30 372: 48 1b sub r20, r24 374: 59 0b sbc r21, r25 376: bc 01 movw r22, r24 378: 87 e2 ldi r24, 0x27 ; 39 37a: 91 e0 ldi r25, 0x01 ; 1 37c: 0c 94 82 00 jmp 0x104 ; 0x104 <_ZN5Print5writeEPKhj> } 380: 80 e0 ldi r24, 0x00 ; 0 382: 90 e0 ldi r25, 0x00 ; 0 384: 08 95 ret 00000386 <__cxa_pure_virtual>: extern "C" void __cxa_deleted_virtual(void) __attribute__ ((__noreturn__)); void __cxa_pure_virtual(void) { // We might want to write some diagnostics to uart in this case //std::terminate(); abort(); 386: 0e 94 21 04 call 0x842 ; 0x842 0000038a <__vector_19>: #elif defined(USART_UDRE_vect) ISR(USART_UDRE_vect) #else #error "Don't know what the Data Register Empty vector is called for Serial" #endif { 38a: 1f 92 push r1 38c: 0f 92 push r0 38e: 0f b6 in r0, 0x3f ; 63 390: 0f 92 push r0 392: 11 24 eor r1, r1 394: 2f 93 push r18 396: 3f 93 push r19 398: 4f 93 push r20 39a: 5f 93 push r21 39c: 6f 93 push r22 39e: 7f 93 push r23 3a0: 8f 93 push r24 3a2: 9f 93 push r25 3a4: af 93 push r26 3a6: bf 93 push r27 3a8: ef 93 push r30 3aa: ff 93 push r31 Serial._tx_udr_empty_irq(); 3ac: 87 e2 ldi r24, 0x27 ; 39 3ae: 91 e0 ldi r25, 0x01 ; 1 3b0: 0e 94 f8 00 call 0x1f0 ; 0x1f0 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> } 3b4: ff 91 pop r31 3b6: ef 91 pop r30 3b8: bf 91 pop r27 3ba: af 91 pop r26 3bc: 9f 91 pop r25 3be: 8f 91 pop r24 3c0: 7f 91 pop r23 3c2: 6f 91 pop r22 3c4: 5f 91 pop r21 3c6: 4f 91 pop r20 3c8: 3f 91 pop r19 3ca: 2f 91 pop r18 3cc: 0f 90 pop r0 3ce: 0f be out 0x3f, r0 ; 63 3d0: 0f 90 pop r0 3d2: 1f 90 pop r1 3d4: 18 95 reti 000003d6 <__vector_18>: #elif defined(USART_RXC_vect) ISR(USART_RXC_vect) // ATmega8 #else #error "Don't know what the Data Received vector is called for Serial" #endif { 3d6: 1f 92 push r1 3d8: 0f 92 push r0 3da: 0f b6 in r0, 0x3f ; 63 3dc: 0f 92 push r0 3de: 11 24 eor r1, r1 3e0: 2f 93 push r18 3e2: 8f 93 push r24 3e4: 9f 93 push r25 3e6: ef 93 push r30 3e8: ff 93 push r31 // Actual interrupt handlers ////////////////////////////////////////////////////////////// void HardwareSerial::_rx_complete_irq(void) { if (bit_is_clear(*_ucsra, UPE0)) { 3ea: e0 91 37 01 lds r30, 0x0137 3ee: f0 91 38 01 lds r31, 0x0138 3f2: 80 81 ld r24, Z 3f4: e0 91 3d 01 lds r30, 0x013D 3f8: f0 91 3e 01 lds r31, 0x013E 3fc: 82 fd sbrc r24, 2 3fe: 12 c0 rjmp .+36 ; 0x424 <__LOCK_REGION_LENGTH__+0x24> // No Parity error, read byte and store it in the buffer if there is // room unsigned char c = *_udr; 400: 90 81 ld r25, Z rx_buffer_index_t i = (unsigned int)(_rx_buffer_head + 1) % SERIAL_RX_BUFFER_SIZE; 402: 80 91 40 01 lds r24, 0x0140 406: 8f 5f subi r24, 0xFF ; 255 408: 8f 73 andi r24, 0x3F ; 63 // if we should be storing the received character into the location // just before the tail (meaning that the head would advance to the // current location of the tail), we're about to overflow the buffer // and so we don't write the character or advance the head. if (i != _rx_buffer_tail) { 40a: 20 91 41 01 lds r18, 0x0141 40e: 82 17 cp r24, r18 410: 51 f0 breq .+20 ; 0x426 <__LOCK_REGION_LENGTH__+0x26> _rx_buffer[_rx_buffer_head] = c; 412: e0 91 40 01 lds r30, 0x0140 416: f0 e0 ldi r31, 0x00 ; 0 418: e9 5d subi r30, 0xD9 ; 217 41a: fe 4f sbci r31, 0xFE ; 254 41c: 95 8f std Z+29, r25 ; 0x1d _rx_buffer_head = i; 41e: 80 93 40 01 sts 0x0140, r24 422: 01 c0 rjmp .+2 ; 0x426 <__LOCK_REGION_LENGTH__+0x26> } } else { // Parity error, read byte but discard it *_udr; 424: 80 81 ld r24, Z Serial._rx_complete_irq(); } 426: ff 91 pop r31 428: ef 91 pop r30 42a: 9f 91 pop r25 42c: 8f 91 pop r24 42e: 2f 91 pop r18 430: 0f 90 pop r0 432: 0f be out 0x3f, r0 ; 63 434: 0f 90 pop r0 436: 1f 90 pop r1 438: 18 95 reti 0000043a <__vector_16>: #if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ISR(TIM0_OVF_vect) #else ISR(TIMER0_OVF_vect) #endif { 43a: 1f 92 push r1 43c: 0f 92 push r0 43e: 0f b6 in r0, 0x3f ; 63 440: 0f 92 push r0 442: 11 24 eor r1, r1 444: 2f 93 push r18 446: 3f 93 push r19 448: 8f 93 push r24 44a: 9f 93 push r25 44c: af 93 push r26 44e: bf 93 push r27 // copy these to local variables so they can be stored in registers // (volatile variables must be read from memory on every access) unsigned long m = timer0_millis; 450: 80 91 1b 01 lds r24, 0x011B 454: 90 91 1c 01 lds r25, 0x011C 458: a0 91 1d 01 lds r26, 0x011D 45c: b0 91 1e 01 lds r27, 0x011E unsigned char f = timer0_fract; 460: 30 91 1a 01 lds r19, 0x011A m += MILLIS_INC; f += FRACT_INC; 464: 23 e0 ldi r18, 0x03 ; 3 466: 23 0f add r18, r19 if (f >= FRACT_MAX) { 468: 2d 37 cpi r18, 0x7D ; 125 46a: 20 f4 brcc .+8 ; 0x474 <__vector_16+0x3a> // copy these to local variables so they can be stored in registers // (volatile variables must be read from memory on every access) unsigned long m = timer0_millis; unsigned char f = timer0_fract; m += MILLIS_INC; 46c: 01 96 adiw r24, 0x01 ; 1 46e: a1 1d adc r26, r1 470: b1 1d adc r27, r1 472: 05 c0 rjmp .+10 ; 0x47e <__vector_16+0x44> f += FRACT_INC; if (f >= FRACT_MAX) { f -= FRACT_MAX; 474: 26 e8 ldi r18, 0x86 ; 134 476: 23 0f add r18, r19 m += 1; 478: 02 96 adiw r24, 0x02 ; 2 47a: a1 1d adc r26, r1 47c: b1 1d adc r27, r1 } timer0_fract = f; 47e: 20 93 1a 01 sts 0x011A, r18 timer0_millis = m; 482: 80 93 1b 01 sts 0x011B, r24 486: 90 93 1c 01 sts 0x011C, r25 48a: a0 93 1d 01 sts 0x011D, r26 48e: b0 93 1e 01 sts 0x011E, r27 timer0_overflow_count++; 492: 80 91 1f 01 lds r24, 0x011F 496: 90 91 20 01 lds r25, 0x0120 49a: a0 91 21 01 lds r26, 0x0121 49e: b0 91 22 01 lds r27, 0x0122 4a2: 01 96 adiw r24, 0x01 ; 1 4a4: a1 1d adc r26, r1 4a6: b1 1d adc r27, r1 4a8: 80 93 1f 01 sts 0x011F, r24 4ac: 90 93 20 01 sts 0x0120, r25 4b0: a0 93 21 01 sts 0x0121, r26 4b4: b0 93 22 01 sts 0x0122, r27 } 4b8: bf 91 pop r27 4ba: af 91 pop r26 4bc: 9f 91 pop r25 4be: 8f 91 pop r24 4c0: 3f 91 pop r19 4c2: 2f 91 pop r18 4c4: 0f 90 pop r0 4c6: 0f be out 0x3f, r0 ; 63 4c8: 0f 90 pop r0 4ca: 1f 90 pop r1 4cc: 18 95 reti 000004ce : countPulseASM: .LM0: .LFBB1: push r12 ; ; 130 pushqi1/1 [length = 1] 4ce: cf 92 push r12 push r13 ; ; 131 pushqi1/1 [length = 1] 4d0: df 92 push r13 push r14 ; ; 132 pushqi1/1 [length = 1] 4d2: ef 92 push r14 push r15 ; ; 133 pushqi1/1 [length = 1] 4d4: ff 92 push r15 push r16 ; ; 134 pushqi1/1 [length = 1] 4d6: 0f 93 push r16 push r17 ; ; 135 pushqi1/1 [length = 1] 4d8: 1f 93 push r17 /* prologue: function */ /* frame size = 0 */ /* stack size = 6 */ .L__stack_usage = 6 mov r30,r24 ; port, port ; 2 *movhi/1 [length = 2] 4da: e8 2f mov r30, r24 mov r31,r25 ; port, port 4dc: f9 2f mov r31, r25 /* unsigned long width = 0; *** // wait for any previous pulse to end *** while ((*port & bit) == stateMask) */ .LM1: rjmp .L2 ; ; 181 jump [length = 1] 4de: 05 c0 rjmp .+10 ; 0x4ea .L4: /* if (--maxloops == 0) */ .LM2: subi r16,1 ; maxloops, ; 17 addsi3/2 [length = 4] 4e0: 01 50 subi r16, 0x01 ; 1 sbc r17, r1 ; maxloops 4e2: 11 09 sbc r17, r1 sbc r18, r1 ; maxloops 4e4: 21 09 sbc r18, r1 sbc r19, r1 ; maxloops 4e6: 31 09 sbc r19, r1 breq .L13 ; , ; 19 branch [length = 1] 4e8: 61 f1 breq .+88 ; 0x542 .L2: /* if (--maxloops == 0) */ .LM3: ld r25,Z ; D.1554, *port_7(D) ; 22 movqi_insn/4 [length = 1] 4ea: 90 81 ld r25, Z and r25,r22 ; D.1554, bit ; 24 andqi3/1 [length = 1] 4ec: 96 23 and r25, r22 cp r25,r20 ; D.1554, stateMask ; 25 *cmpqi/2 [length = 1] 4ee: 94 17 cp r25, r20 breq .L4 ; , ; 26 branch [length = 1] 4f0: b9 f3 breq .-18 ; 0x4e0 rjmp .L6 ; ; 184 jump [length = 1] 4f2: 05 c0 rjmp .+10 ; 0x4fe *** // wait for the pulse to start *** while ((*port & bit) != stateMask) *** if (--maxloops == 0) */ .LM4: subi r16,1 ; maxloops, ; 31 addsi3/2 [length = 4] 4f4: 01 50 subi r16, 0x01 ; 1 sbc r17, r1 ; maxloops 4f6: 11 09 sbc r17, r1 sbc r18, r1 ; maxloops 4f8: 21 09 sbc r18, r1 sbc r19, r1 ; maxloops 4fa: 31 09 sbc r19, r1 breq .L13 ; , ; 33 branch [length = 1] 4fc: 11 f1 breq .+68 ; 0x542 .L6: /* if (--maxloops == 0) */ .LM5: ld r25,Z ; D.1554, *port_7(D) ; 41 movqi_insn/4 [length = 1] 4fe: 90 81 ld r25, Z and r25,r22 ; D.1554, bit ; 43 andqi3/1 [length = 1] 500: 96 23 and r25, r22 cpse r25,r20 ; D.1554, stateMask ; 44 enable_interrupt-3 [length = 1] 502: 94 13 cpse r25, r20 rjmp .L7 ; 504: f7 cf rjmp .-18 ; 0x4f4 mov r12, r1 ; width ; 7 *movsi/2 [length = 4] 506: c1 2c mov r12, r1 mov r13, r1 ; width 508: d1 2c mov r13, r1 mov r14, r1 ; width 50a: e1 2c mov r14, r1 mov r15, r1 ; width 50c: f1 2c mov r15, r1 rjmp .L9 ; ; 186 jump [length = 1] 50e: 0a c0 rjmp .+20 ; 0x524 *** // wait for the pulse to stop *** while ((*port & bit) == stateMask) { *** if (++width == maxloops) */ .LM6: ldi r24,-1 ; , ; 50 addsi3/3 [length = 5] 510: 8f ef ldi r24, 0xFF ; 255 sub r12,r24 ; width, 512: c8 1a sub r12, r24 sbc r13,r24 ; width, 514: d8 0a sbc r13, r24 sbc r14,r24 ; width, 516: e8 0a sbc r14, r24 sbc r15,r24 ; width, 518: f8 0a sbc r15, r24 cp r16,r12 ; maxloops, width ; 51 *cmpsi/2 [length = 4] 51a: 0c 15 cp r16, r12 cpc r17,r13 ; maxloops, width 51c: 1d 05 cpc r17, r13 cpc r18,r14 ; maxloops, width 51e: 2e 05 cpc r18, r14 cpc r19,r15 ; maxloops, width 520: 3f 05 cpc r19, r15 breq .L13 ; , ; 52 branch [length = 1] 522: 79 f0 breq .+30 ; 0x542 .L9: /* if (++width == maxloops) */ .LM7: ld r24,Z ; D.1554, *port_7(D) ; 60 movqi_insn/4 [length = 1] 524: 80 81 ld r24, Z and r24,r22 ; D.1554, bit ; 62 andqi3/1 [length = 1] 526: 86 23 and r24, r22 cp r24,r20 ; D.1554, stateMask ; 63 *cmpqi/2 [length = 1] 528: 84 17 cp r24, r20 breq .L10 ; , ; 64 branch [length = 1] 52a: 91 f3 breq .-28 ; 0x510 /* return 0; *** } *** return width; */ .LM8: mov r22,r12 ; D.1553, width ; 108 movqi_insn/1 [length = 1] 52c: 6c 2d mov r22, r12 mov r23,r13 ; D.1553, width ; 109 movqi_insn/1 [length = 1] 52e: 7d 2d mov r23, r13 mov r24,r14 ; D.1553, width ; 110 movqi_insn/1 [length = 1] 530: 8e 2d mov r24, r14 mov r25,r15 ; D.1553, width ; 111 movqi_insn/1 [length = 1] 532: 9f 2d mov r25, r15 /* epilogue start */ .LM9: pop r17 ; ; 171 popqi [length = 1] 534: 1f 91 pop r17 pop r16 ; ; 172 popqi [length = 1] 536: 0f 91 pop r16 pop r15 ; ; 173 popqi [length = 1] 538: ff 90 pop r15 pop r14 ; ; 174 popqi [length = 1] 53a: ef 90 pop r14 pop r13 ; ; 175 popqi [length = 1] 53c: df 90 pop r13 pop r12 ; ; 176 popqi [length = 1] 53e: cf 90 pop r12 ret ; 177 return_from_epilogue [length = 1] 540: 08 95 ret .L13: .LM10: ldi r22,0 ; D.1553 ; 120 movqi_insn/1 [length = 1] 542: 60 e0 ldi r22, 0x00 ; 0 ldi r23,0 ; D.1553 ; 121 movqi_insn/1 [length = 1] 544: 70 e0 ldi r23, 0x00 ; 0 ldi r24,0 ; D.1553 ; 122 movqi_insn/1 [length = 1] 546: 80 e0 ldi r24, 0x00 ; 0 ldi r25,0 ; D.1553 ; 123 movqi_insn/1 [length = 1] 548: 90 e0 ldi r25, 0x00 ; 0 /* epilogue start */ .LM11: pop r17 ; ; 138 popqi [length = 1] 54a: 1f 91 pop r17 pop r16 ; ; 139 popqi [length = 1] 54c: 0f 91 pop r16 pop r15 ; ; 140 popqi [length = 1] 54e: ff 90 pop r15 pop r14 ; ; 141 popqi [length = 1] 550: ef 90 pop r14 pop r13 ; ; 142 popqi [length = 1] 552: df 90 pop r13 pop r12 ; ; 143 popqi [length = 1] 554: cf 90 pop r12 ret ; 144 return_from_epilogue [length = 1] 556: 08 95 ret 00000558
: void setupUSB() __attribute__((weak)); void setupUSB() { } int main(void) { 558: cf 93 push r28 55a: df 93 push r29 55c: cd b7 in r28, 0x3d ; 61 55e: de b7 in r29, 0x3e ; 62 560: a1 97 sbiw r28, 0x21 ; 33 562: 0f b6 in r0, 0x3f ; 63 564: f8 94 cli 566: de bf out 0x3e, r29 ; 62 568: 0f be out 0x3f, r0 ; 63 56a: cd bf out 0x3d, r28 ; 61 void init() { // this needs to be called before setup() or some functions won't // work there sei(); 56c: 78 94 sei // on the ATmega168, timer 0 is also used for fast hardware pwm // (using phase-correct PWM would mean that timer 0 overflowed half as often // resulting in different millis() behavior on the ATmega8 and ATmega168) #if defined(TCCR0A) && defined(WGM01) sbi(TCCR0A, WGM01); 56e: 84 b5 in r24, 0x24 ; 36 570: 82 60 ori r24, 0x02 ; 2 572: 84 bd out 0x24, r24 ; 36 sbi(TCCR0A, WGM00); 574: 84 b5 in r24, 0x24 ; 36 576: 81 60 ori r24, 0x01 ; 1 578: 84 bd out 0x24, r24 ; 36 // this combination is for the standard atmega8 sbi(TCCR0, CS01); sbi(TCCR0, CS00); #elif defined(TCCR0B) && defined(CS01) && defined(CS00) // this combination is for the standard 168/328/1280/2560 sbi(TCCR0B, CS01); 57a: 85 b5 in r24, 0x25 ; 37 57c: 82 60 ori r24, 0x02 ; 2 57e: 85 bd out 0x25, r24 ; 37 sbi(TCCR0B, CS00); 580: 85 b5 in r24, 0x25 ; 37 582: 81 60 ori r24, 0x01 ; 1 584: 85 bd out 0x25, r24 ; 37 // enable timer 0 overflow interrupt #if defined(TIMSK) && defined(TOIE0) sbi(TIMSK, TOIE0); #elif defined(TIMSK0) && defined(TOIE0) sbi(TIMSK0, TOIE0); 586: 80 91 6e 00 lds r24, 0x006E 58a: 81 60 ori r24, 0x01 ; 1 58c: 80 93 6e 00 sts 0x006E, r24 // this is better for motors as it ensures an even waveform // note, however, that fast pwm mode can achieve a frequency of up // 8 MHz (with a 16 MHz clock) at 50% duty cycle #if defined(TCCR1B) && defined(CS11) && defined(CS10) TCCR1B = 0; 590: 10 92 81 00 sts 0x0081, r1 // set timer 1 prescale factor to 64 sbi(TCCR1B, CS11); 594: 80 91 81 00 lds r24, 0x0081 598: 82 60 ori r24, 0x02 ; 2 59a: 80 93 81 00 sts 0x0081, r24 #if F_CPU >= 8000000L sbi(TCCR1B, CS10); 59e: 80 91 81 00 lds r24, 0x0081 5a2: 81 60 ori r24, 0x01 ; 1 5a4: 80 93 81 00 sts 0x0081, r24 sbi(TCCR1, CS10); #endif #endif // put timer 1 in 8-bit phase correct pwm mode #if defined(TCCR1A) && defined(WGM10) sbi(TCCR1A, WGM10); 5a8: 80 91 80 00 lds r24, 0x0080 5ac: 81 60 ori r24, 0x01 ; 1 5ae: 80 93 80 00 sts 0x0080, r24 // set timer 2 prescale factor to 64 #if defined(TCCR2) && defined(CS22) sbi(TCCR2, CS22); #elif defined(TCCR2B) && defined(CS22) sbi(TCCR2B, CS22); 5b2: 80 91 b1 00 lds r24, 0x00B1 5b6: 84 60 ori r24, 0x04 ; 4 5b8: 80 93 b1 00 sts 0x00B1, r24 // configure timer 2 for phase correct pwm (8-bit) #if defined(TCCR2) && defined(WGM20) sbi(TCCR2, WGM20); #elif defined(TCCR2A) && defined(WGM20) sbi(TCCR2A, WGM20); 5bc: 80 91 b0 00 lds r24, 0x00B0 5c0: 81 60 ori r24, 0x01 ; 1 5c2: 80 93 b0 00 sts 0x00B0, r24 #endif #if defined(ADCSRA) // set a2d prescaler so we are inside the desired 50-200 KHz range. #if F_CPU >= 16000000 // 16 MHz / 128 = 125 KHz sbi(ADCSRA, ADPS2); 5c6: 80 91 7a 00 lds r24, 0x007A 5ca: 84 60 ori r24, 0x04 ; 4 5cc: 80 93 7a 00 sts 0x007A, r24 sbi(ADCSRA, ADPS1); 5d0: 80 91 7a 00 lds r24, 0x007A 5d4: 82 60 ori r24, 0x02 ; 2 5d6: 80 93 7a 00 sts 0x007A, r24 sbi(ADCSRA, ADPS0); 5da: 80 91 7a 00 lds r24, 0x007A 5de: 81 60 ori r24, 0x01 ; 1 5e0: 80 93 7a 00 sts 0x007A, r24 cbi(ADCSRA, ADPS2); cbi(ADCSRA, ADPS1); sbi(ADCSRA, ADPS0); #endif // enable a2d conversions sbi(ADCSRA, ADEN); 5e4: 80 91 7a 00 lds r24, 0x007A 5e8: 80 68 ori r24, 0x80 ; 128 5ea: 80 93 7a 00 sts 0x007A, r24 // here so they can be used as normal digital i/o; they will be // reconnected in Serial.begin() #if defined(UCSRB) UCSRB = 0; #elif defined(UCSR0B) UCSR0B = 0; 5ee: 10 92 c1 00 sts 0x00C1, r1 #include "wiring_private.h" #include "pins_arduino.h" void pinMode(uint8_t pin, uint8_t mode) { uint8_t bit = digitalPinToBitMask(pin); 5f2: ec e9 ldi r30, 0x9C ; 156 5f4: f0 e0 ldi r31, 0x00 ; 0 5f6: 24 91 lpm r18, Z uint8_t port = digitalPinToPort(pin); 5f8: e8 e8 ldi r30, 0x88 ; 136 5fa: f0 e0 ldi r31, 0x00 ; 0 5fc: 84 91 lpm r24, Z volatile uint8_t *reg, *out; if (port == NOT_A_PIN) return; 5fe: 88 23 and r24, r24 600: c9 f0 breq .+50 ; 0x634 // JWS: can I let the optimizer do this? reg = portModeRegister(port); 602: 90 e0 ldi r25, 0x00 ; 0 604: 88 0f add r24, r24 606: 99 1f adc r25, r25 608: fc 01 movw r30, r24 60a: ee 58 subi r30, 0x8E ; 142 60c: ff 4f sbci r31, 0xFF ; 255 60e: 45 91 lpm r20, Z+ 610: 54 91 lpm r21, Z out = portOutputRegister(port); 612: fc 01 movw r30, r24 614: e8 59 subi r30, 0x98 ; 152 616: ff 4f sbci r31, 0xFF ; 255 618: a5 91 lpm r26, Z+ 61a: b4 91 lpm r27, Z if (mode == INPUT) { uint8_t oldSREG = SREG; 61c: 9f b7 in r25, 0x3f ; 63 cli(); 61e: f8 94 cli *reg &= ~bit; 620: fa 01 movw r30, r20 622: 80 81 ld r24, Z 624: 20 95 com r18 626: 82 23 and r24, r18 628: 80 83 st Z, r24 *out &= ~bit; 62a: 8c 91 ld r24, X 62c: e2 2f mov r30, r18 62e: e8 23 and r30, r24 630: ec 93 st X, r30 SREG = oldSREG; 632: 9f bf out 0x3f, r25 ; 63 void HardwareSerial::begin(unsigned long baud, byte config) { // Try u2x mode first uint16_t baud_setting = (F_CPU / 4 / baud - 1) / 2; *_ucsra = 1 << U2X0; 634: e0 91 37 01 lds r30, 0x0137 638: f0 91 38 01 lds r31, 0x0138 63c: 82 e0 ldi r24, 0x02 ; 2 63e: 80 83 st Z, r24 *_ucsra = 0; baud_setting = (F_CPU / 8 / baud - 1) / 2; } // assign the baud_setting, a.k.a. ubrr (USART Baud Rate Register) *_ubrrh = baud_setting >> 8; 640: e0 91 33 01 lds r30, 0x0133 644: f0 91 34 01 lds r31, 0x0134 648: 10 82 st Z, r1 *_ubrrl = baud_setting; 64a: e0 91 35 01 lds r30, 0x0135 64e: f0 91 36 01 lds r31, 0x0136 652: 8f ec ldi r24, 0xCF ; 207 654: 80 83 st Z, r24 _written = false; 656: 10 92 3f 01 sts 0x013F, r1 //set the data bits, parity, and stop bits #if defined(__AVR_ATmega8__) config |= 0x80; // select UCSRC register (shared with UBRRH) #endif *_ucsrc = config; 65a: e0 91 3b 01 lds r30, 0x013B 65e: f0 91 3c 01 lds r31, 0x013C 662: 86 e0 ldi r24, 0x06 ; 6 664: 80 83 st Z, r24 sbi(*_ucsrb, RXEN0); 666: e0 91 39 01 lds r30, 0x0139 66a: f0 91 3a 01 lds r31, 0x013A 66e: 80 81 ld r24, Z 670: 80 61 ori r24, 0x10 ; 16 672: 80 83 st Z, r24 sbi(*_ucsrb, TXEN0); 674: e0 91 39 01 lds r30, 0x0139 678: f0 91 3a 01 lds r31, 0x013A 67c: 80 81 ld r24, Z 67e: 88 60 ori r24, 0x08 ; 8 680: 80 83 st Z, r24 sbi(*_ucsrb, RXCIE0); 682: e0 91 39 01 lds r30, 0x0139 686: f0 91 3a 01 lds r31, 0x013A 68a: 80 81 ld r24, Z 68c: 80 68 ori r24, 0x80 ; 128 68e: 80 83 st Z, r24 cbi(*_ucsrb, UDRIE0); 690: e0 91 39 01 lds r30, 0x0139 694: f0 91 3a 01 lds r31, 0x013A 698: 80 81 ld r24, Z 69a: 8f 7d andi r24, 0xDF ; 223 69c: 80 83 st Z, r24 unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout) { // cache the port and bit of the pin in order to speed up the // pulse width measuring loop and achieve finer resolution. calling // digitalRead() instead yields much coarser resolution. uint8_t bit = digitalPinToBitMask(pin); 69e: 2c e9 ldi r18, 0x9C ; 156 6a0: 22 2e mov r2, r18 6a2: 20 e0 ldi r18, 0x00 ; 0 6a4: 32 2e mov r3, r18 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; 6a6: 3a e0 ldi r19, 0x0A ; 10 6a8: 83 2e mov r8, r19 6aa: 91 2c mov r9, r1 6ac: a1 2c mov r10, r1 6ae: b1 2c mov r11, r1 6b0: f1 01 movw r30, r2 6b2: 64 91 lpm r22, Z uint8_t port = digitalPinToPort(pin); 6b4: e8 e8 ldi r30, 0x88 ; 136 6b6: f0 e0 ldi r31, 0x00 ; 0 6b8: a4 91 lpm r26, Z // convert the timeout from microseconds to a number of times through // the initial loop; it takes approximately 16 clock cycles per iteration unsigned long maxloops = microsecondsToClockCycles(timeout)/16; unsigned long width = countPulseASM(portInputRegister(port), bit, stateMask, maxloops); 6ba: b0 e0 ldi r27, 0x00 ; 0 6bc: aa 0f add r26, r26 6be: bb 1f adc r27, r27 6c0: a4 58 subi r26, 0x84 ; 132 6c2: bf 4f sbci r27, 0xFF ; 255 6c4: fd 01 movw r30, r26 6c6: 85 91 lpm r24, Z+ 6c8: 94 91 lpm r25, Z 6ca: 00 e4 ldi r16, 0x40 ; 64 6cc: 12 e4 ldi r17, 0x42 ; 66 6ce: 2f e0 ldi r18, 0x0F ; 15 6d0: 30 e0 ldi r19, 0x00 ; 0 6d2: 46 2f mov r20, r22 6d4: 0e 94 67 02 call 0x4ce ; 0x4ce // prevent clockCyclesToMicroseconds to return bogus values if countPulseASM timed out if (width) 6d8: 61 15 cp r22, r1 6da: 71 05 cpc r23, r1 6dc: 81 05 cpc r24, r1 6de: 91 05 cpc r25, r1 6e0: 49 f0 breq .+18 ; 0x6f4 return clockCyclesToMicroseconds(width * 16 + 16); 6e2: dc 01 movw r26, r24 6e4: cb 01 movw r24, r22 6e6: 01 96 adiw r24, 0x01 ; 1 6e8: a1 1d adc r26, r1 6ea: b1 1d adc r27, r1 6ec: 9c 01 movw r18, r24 6ee: ad 01 movw r20, r26 6f0: 5f 70 andi r21, 0x0F ; 15 6f2: 03 c0 rjmp .+6 ; 0x6fa else return 0; 6f4: 20 e0 ldi r18, 0x00 ; 0 6f6: 30 e0 ldi r19, 0x00 ; 0 6f8: a9 01 movw r20, r18 // initialize serial communication: Serial.begin(9600); } void loop() { duration=pulseIn(pingPin,HIGH); 6fa: 20 93 23 01 sts 0x0123, r18 6fe: 30 93 24 01 sts 0x0124, r19 702: 40 93 25 01 sts 0x0125, r20 706: 50 93 26 01 sts 0x0126, r21 size_t Print::printNumber(unsigned long n, uint8_t base) { char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. char *str = &buf[sizeof(buf) - 1]; *str = '\0'; 70a: 19 a2 std Y+33, r1 ; 0x21 70c: 8e 01 movw r16, r28 70e: 0f 5d subi r16, 0xDF ; 223 710: 1f 4f sbci r17, 0xFF ; 255 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; n /= base; 712: ca 01 movw r24, r20 714: b9 01 movw r22, r18 716: a5 01 movw r20, r10 718: 94 01 movw r18, r8 71a: 0e 94 f9 03 call 0x7f2 ; 0x7f2 <__udivmodsi4> *--str = c < 10 ? c + '0' : c + 'A' - 10; 71e: 60 5d subi r22, 0xD0 ; 208 720: f8 01 movw r30, r16 722: 62 93 st -Z, r22 724: 8f 01 movw r16, r30 *str = '\0'; // prevent crash if called with base == 1 if (base < 2) base = 10; do { 726: 21 15 cp r18, r1 728: 31 05 cpc r19, r1 72a: 41 05 cpc r20, r1 72c: 51 05 cpc r21, r1 72e: 89 f7 brne .-30 ; 0x712 n /= base; *--str = c < 10 ? c + '0' : c + 'A' - 10; } while(n); return write(str); 730: cf 01 movw r24, r30 732: 0e 94 b1 01 call 0x362 ; 0x362 <_ZN5Print5writeEPKc.constprop.10> return write(s.c_str(), s.length()); } size_t Print::print(const char str[]) { return write(str); 736: 82 e1 ldi r24, 0x12 ; 18 738: 91 e0 ldi r25, 0x01 ; 1 73a: 0e 94 b1 01 call 0x362 ; 0x362 <_ZN5Print5writeEPKc.constprop.10> return x.printTo(*this); } size_t Print::println(void) { return write("\r\n"); 73e: 86 e1 ldi r24, 0x16 ; 22 740: 91 e0 ldi r25, 0x01 ; 1 742: 0e 94 b1 01 call 0x362 ; 0x362 <_ZN5Print5writeEPKc.constprop.10> return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond()); } void delay(unsigned long ms) { uint32_t start = micros(); 746: 0e 94 8c 01 call 0x318 ; 0x318 74a: 6b 01 movw r12, r22 74c: 7c 01 movw r14, r24 74e: 84 e6 ldi r24, 0x64 ; 100 750: 48 2e mov r4, r24 752: 51 2c mov r5, r1 754: 61 2c mov r6, r1 756: 71 2c mov r7, r1 while (ms > 0) { yield(); while ( ms > 0 && (micros() - start) >= 1000) { 758: 0e 94 8c 01 call 0x318 ; 0x318 75c: dc 01 movw r26, r24 75e: cb 01 movw r24, r22 760: 8c 19 sub r24, r12 762: 9d 09 sbc r25, r13 764: ae 09 sbc r26, r14 766: bf 09 sbc r27, r15 768: 88 3e cpi r24, 0xE8 ; 232 76a: 93 40 sbci r25, 0x03 ; 3 76c: a1 05 cpc r26, r1 76e: b1 05 cpc r27, r1 770: 58 f0 brcs .+22 ; 0x788 ms--; 772: f1 e0 ldi r31, 0x01 ; 1 774: 4f 1a sub r4, r31 776: 51 08 sbc r5, r1 778: 61 08 sbc r6, r1 77a: 71 08 sbc r7, r1 start += 1000; 77c: 28 ee ldi r18, 0xE8 ; 232 77e: c2 0e add r12, r18 780: 23 e0 ldi r18, 0x03 ; 3 782: d2 1e adc r13, r18 784: e1 1c adc r14, r1 786: f1 1c adc r15, r1 { uint32_t start = micros(); while (ms > 0) { yield(); while ( ms > 0 && (micros() - start) >= 1000) { 788: 41 14 cp r4, r1 78a: 51 04 cpc r5, r1 78c: 61 04 cpc r6, r1 78e: 71 04 cpc r7, r1 790: 19 f7 brne .-58 ; 0x758 setup(); for (;;) { loop(); if (serialEventRun) serialEventRun(); 792: 0e 94 82 01 call 0x304 ; 0x304 <_Z14serialEventRunv> 796: 8c cf rjmp .-232 ; 0x6b0 00000798 <_GLOBAL__sub_I___vector_18>: size_t printNumber(unsigned long, uint8_t); size_t printFloat(double, uint8_t); protected: void setWriteError(int err = 1) { write_error = err; } public: Print() : write_error(0) {} 798: e7 e2 ldi r30, 0x27 ; 39 79a: f1 e0 ldi r31, 0x01 ; 1 79c: 13 82 std Z+3, r1 ; 0x03 79e: 12 82 std Z+2, r1 ; 0x02 public: virtual int available() = 0; virtual int read() = 0; virtual int peek() = 0; Stream() {_timeout=1000;} 7a0: 88 ee ldi r24, 0xE8 ; 232 7a2: 93 e0 ldi r25, 0x03 ; 3 7a4: a0 e0 ldi r26, 0x00 ; 0 7a6: b0 e0 ldi r27, 0x00 ; 0 7a8: 84 83 std Z+4, r24 ; 0x04 7aa: 95 83 std Z+5, r25 ; 0x05 7ac: a6 83 std Z+6, r26 ; 0x06 7ae: b7 83 std Z+7, r27 ; 0x07 volatile uint8_t *ucsrc, volatile uint8_t *udr) : _ubrrh(ubrrh), _ubrrl(ubrrl), _ucsra(ucsra), _ucsrb(ucsrb), _ucsrc(ucsrc), _udr(udr), _rx_buffer_head(0), _rx_buffer_tail(0), _tx_buffer_head(0), _tx_buffer_tail(0) 7b0: 84 e0 ldi r24, 0x04 ; 4 7b2: 91 e0 ldi r25, 0x01 ; 1 7b4: 91 83 std Z+1, r25 ; 0x01 7b6: 80 83 st Z, r24 7b8: 85 ec ldi r24, 0xC5 ; 197 7ba: 90 e0 ldi r25, 0x00 ; 0 7bc: 95 87 std Z+13, r25 ; 0x0d 7be: 84 87 std Z+12, r24 ; 0x0c 7c0: 84 ec ldi r24, 0xC4 ; 196 7c2: 90 e0 ldi r25, 0x00 ; 0 7c4: 97 87 std Z+15, r25 ; 0x0f 7c6: 86 87 std Z+14, r24 ; 0x0e 7c8: 80 ec ldi r24, 0xC0 ; 192 7ca: 90 e0 ldi r25, 0x00 ; 0 7cc: 91 8b std Z+17, r25 ; 0x11 7ce: 80 8b std Z+16, r24 ; 0x10 7d0: 81 ec ldi r24, 0xC1 ; 193 7d2: 90 e0 ldi r25, 0x00 ; 0 7d4: 93 8b std Z+19, r25 ; 0x13 7d6: 82 8b std Z+18, r24 ; 0x12 7d8: 82 ec ldi r24, 0xC2 ; 194 7da: 90 e0 ldi r25, 0x00 ; 0 7dc: 95 8b std Z+21, r25 ; 0x15 7de: 84 8b std Z+20, r24 ; 0x14 7e0: 86 ec ldi r24, 0xC6 ; 198 7e2: 90 e0 ldi r25, 0x00 ; 0 7e4: 97 8b std Z+23, r25 ; 0x17 7e6: 86 8b std Z+22, r24 ; 0x16 7e8: 11 8e std Z+25, r1 ; 0x19 7ea: 12 8e std Z+26, r1 ; 0x1a 7ec: 13 8e std Z+27, r1 ; 0x1b 7ee: 14 8e std Z+28, r1 ; 0x1c 7f0: 08 95 ret 000007f2 <__udivmodsi4>: 7f2: a1 e2 ldi r26, 0x21 ; 33 7f4: 1a 2e mov r1, r26 7f6: aa 1b sub r26, r26 7f8: bb 1b sub r27, r27 7fa: fd 01 movw r30, r26 7fc: 0d c0 rjmp .+26 ; 0x818 <__udivmodsi4_ep> 000007fe <__udivmodsi4_loop>: 7fe: aa 1f adc r26, r26 800: bb 1f adc r27, r27 802: ee 1f adc r30, r30 804: ff 1f adc r31, r31 806: a2 17 cp r26, r18 808: b3 07 cpc r27, r19 80a: e4 07 cpc r30, r20 80c: f5 07 cpc r31, r21 80e: 20 f0 brcs .+8 ; 0x818 <__udivmodsi4_ep> 810: a2 1b sub r26, r18 812: b3 0b sbc r27, r19 814: e4 0b sbc r30, r20 816: f5 0b sbc r31, r21 00000818 <__udivmodsi4_ep>: 818: 66 1f adc r22, r22 81a: 77 1f adc r23, r23 81c: 88 1f adc r24, r24 81e: 99 1f adc r25, r25 820: 1a 94 dec r1 822: 69 f7 brne .-38 ; 0x7fe <__udivmodsi4_loop> 824: 60 95 com r22 826: 70 95 com r23 828: 80 95 com r24 82a: 90 95 com r25 82c: 9b 01 movw r18, r22 82e: ac 01 movw r20, r24 830: bd 01 movw r22, r26 832: cf 01 movw r24, r30 834: 08 95 ret 00000836 <__tablejump2__>: 836: ee 0f add r30, r30 838: ff 1f adc r31, r31 83a: 05 90 lpm r0, Z+ 83c: f4 91 lpm r31, Z 83e: e0 2d mov r30, r0 840: 09 94 ijmp 00000842 : 842: 81 e0 ldi r24, 0x01 ; 1 844: 90 e0 ldi r25, 0x00 ; 0 846: f8 94 cli 848: 0c 94 26 04 jmp 0x84c ; 0x84c <_exit> 0000084c <_exit>: 84c: f8 94 cli 0000084e <__stop_program>: 84e: ff cf rjmp .-2 ; 0x84e <__stop_program>