PulseWidthPoll.ino.elf: file format elf32-avr Disassembly of section .text: 00000000 <__vectors>: 0: 0c 94 62 00 jmp 0xc4 ; 0xc4 <__ctors_end> 4: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 8: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 10: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 14: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 18: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 1c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 20: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 24: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 28: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 2c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 30: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 34: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 38: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 3c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 40: 0c 94 6c 02 jmp 0x4d8 ; 0x4d8 <__vector_16> 44: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 48: 0c 94 3a 02 jmp 0x474 ; 0x474 <__vector_18> 4c: 0c 94 14 02 jmp 0x428 ; 0x428 <__vector_19> 50: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 54: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 58: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 5c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 60: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 64: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 00000068 <__trampolines_end>: 68: 00 00 nop 6a: 00 00 nop 6c: 25 00 .word 0x0025 ; ???? 6e: 28 00 .word 0x0028 ; ???? 70: 2b 00 .word 0x002b ; ???? 00000072 : 72: 00 00 00 00 24 00 27 00 2a 00 ....$.'.*. 0000007c : 7c: 00 00 00 00 23 00 26 00 29 00 ....#.&.). 00000086 : 86: 04 04 04 04 04 04 04 04 02 02 02 02 02 02 03 03 ................ 96: 03 03 03 03 .... 0000009a : 9a: 01 02 04 08 10 20 40 80 01 02 04 08 10 20 01 02 ..... @...... .. aa: 04 08 10 20 ... 000000ae : ae: 00 00 00 08 00 02 01 00 00 03 04 07 00 00 00 00 ................ be: 00 00 00 00 .... 000000c2 <__ctors_start>: c2: fb 03 fmulsu r23, r19 000000c4 <__ctors_end>: c4: 11 24 eor r1, r1 c6: 1f be out 0x3f, r1 ; 63 c8: cf ef ldi r28, 0xFF ; 255 ca: d8 e0 ldi r29, 0x08 ; 8 cc: de bf out 0x3e, r29 ; 62 ce: cd bf out 0x3d, r28 ; 61 000000d0 <__do_copy_data>: d0: 11 e0 ldi r17, 0x01 ; 1 d2: a0 e0 ldi r26, 0x00 ; 0 d4: b1 e0 ldi r27, 0x01 ; 1 d6: ee ea ldi r30, 0xAE ; 174 d8: f8 e0 ldi r31, 0x08 ; 8 da: 02 c0 rjmp .+4 ; 0xe0 <__do_copy_data+0x10> dc: 05 90 lpm r0, Z+ de: 0d 92 st X+, r0 e0: aa 31 cpi r26, 0x1A ; 26 e2: b1 07 cpc r27, r17 e4: d9 f7 brne .-10 ; 0xdc <__do_copy_data+0xc> 000000e6 <__do_clear_bss>: e6: 21 e0 ldi r18, 0x01 ; 1 e8: aa e1 ldi r26, 0x1A ; 26 ea: b1 e0 ldi r27, 0x01 ; 1 ec: 01 c0 rjmp .+2 ; 0xf0 <.do_clear_bss_start> 000000ee <.do_clear_bss_loop>: ee: 1d 92 st X+, r1 000000f0 <.do_clear_bss_start>: f0: ac 3c cpi r26, 0xCC ; 204 f2: b2 07 cpc r27, r18 f4: e1 f7 brne .-8 ; 0xee <.do_clear_bss_loop> 000000f6 <__do_global_ctors>: f6: 10 e0 ldi r17, 0x00 ; 0 f8: c2 e6 ldi r28, 0x62 ; 98 fa: d0 e0 ldi r29, 0x00 ; 0 fc: 04 c0 rjmp .+8 ; 0x106 <__do_global_ctors+0x10> fe: 21 97 sbiw r28, 0x01 ; 1 100: fe 01 movw r30, r28 102: 0e 94 4a 04 call 0x894 ; 0x894 <__tablejump2__> 106: c1 36 cpi r28, 0x61 ; 97 108: d1 07 cpc r29, r17 10a: c9 f7 brne .-14 ; 0xfe <__do_global_ctors+0x8> 10c: 0e 94 b6 02 call 0x56c ; 0x56c
110: 0c 94 55 04 jmp 0x8aa ; 0x8aa <_exit> 00000114 <__bad_interrupt>: 114: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 00000118 : SREG = oldSREG; } int digitalRead(uint8_t pin) { uint8_t timer = digitalPinToTimer(pin); 118: e0 eb ldi r30, 0xB0 ; 176 11a: f0 e0 ldi r31, 0x00 ; 0 11c: 84 91 lpm r24, Z uint8_t bit = digitalPinToBitMask(pin); 11e: ec e9 ldi r30, 0x9C ; 156 120: f0 e0 ldi r31, 0x00 ; 0 122: 94 91 lpm r25, Z uint8_t port = digitalPinToPort(pin); 124: e8 e8 ldi r30, 0x88 ; 136 126: f0 e0 ldi r31, 0x00 ; 0 128: e4 91 lpm r30, Z if (port == NOT_A_PIN) return LOW; 12a: ee 23 and r30, r30 12c: b9 f1 breq .+110 ; 0x19c // If the pin that support PWM output, we need to turn it off // before getting a digital reading. if (timer != NOT_ON_TIMER) turnOffPWM(timer); 12e: 88 23 and r24, r24 130: 39 f1 breq .+78 ; 0x180 // //static inline void turnOffPWM(uint8_t timer) __attribute__ ((always_inline)); //static inline void turnOffPWM(uint8_t timer) static void turnOffPWM(uint8_t timer) { switch (timer) 132: 83 30 cpi r24, 0x03 ; 3 134: 91 f0 breq .+36 ; 0x15a 136: 38 f4 brcc .+14 ; 0x146 138: 81 30 cpi r24, 0x01 ; 1 13a: a9 f0 breq .+42 ; 0x166 13c: 82 30 cpi r24, 0x02 ; 2 13e: 01 f5 brne .+64 ; 0x180 #if defined(TCCR0A) && defined(COM0A1) case TIMER0A: cbi(TCCR0A, COM0A1); break; #endif #if defined(TCCR0A) && defined(COM0B1) case TIMER0B: cbi(TCCR0A, COM0B1); break; 140: 84 b5 in r24, 0x24 ; 36 142: 8f 7d andi r24, 0xDF ; 223 144: 12 c0 rjmp .+36 ; 0x16a // //static inline void turnOffPWM(uint8_t timer) __attribute__ ((always_inline)); //static inline void turnOffPWM(uint8_t timer) static void turnOffPWM(uint8_t timer) { switch (timer) 146: 87 30 cpi r24, 0x07 ; 7 148: 91 f0 breq .+36 ; 0x16e 14a: 88 30 cpi r24, 0x08 ; 8 14c: a1 f0 breq .+40 ; 0x176 14e: 84 30 cpi r24, 0x04 ; 4 150: b9 f4 brne .+46 ; 0x180 { #if defined(TCCR1A) && defined(COM1A1) case TIMER1A: cbi(TCCR1A, COM1A1); break; #endif #if defined(TCCR1A) && defined(COM1B1) case TIMER1B: cbi(TCCR1A, COM1B1); break; 152: 80 91 80 00 lds r24, 0x0080 156: 8f 7d andi r24, 0xDF ; 223 158: 03 c0 rjmp .+6 ; 0x160 static void turnOffPWM(uint8_t timer) { switch (timer) { #if defined(TCCR1A) && defined(COM1A1) case TIMER1A: cbi(TCCR1A, COM1A1); break; 15a: 80 91 80 00 lds r24, 0x0080 15e: 8f 77 andi r24, 0x7F ; 127 #endif #if defined(TCCR1A) && defined(COM1B1) case TIMER1B: cbi(TCCR1A, COM1B1); break; 160: 80 93 80 00 sts 0x0080, r24 164: 0d c0 rjmp .+26 ; 0x180 #if defined(TCCR2) && defined(COM21) case TIMER2: cbi(TCCR2, COM21); break; #endif #if defined(TCCR0A) && defined(COM0A1) case TIMER0A: cbi(TCCR0A, COM0A1); break; 166: 84 b5 in r24, 0x24 ; 36 168: 8f 77 andi r24, 0x7F ; 127 #endif #if defined(TCCR0A) && defined(COM0B1) case TIMER0B: cbi(TCCR0A, COM0B1); break; 16a: 84 bd out 0x24, r24 ; 36 16c: 09 c0 rjmp .+18 ; 0x180 #endif #if defined(TCCR2A) && defined(COM2A1) case TIMER2A: cbi(TCCR2A, COM2A1); break; 16e: 80 91 b0 00 lds r24, 0x00B0 172: 8f 77 andi r24, 0x7F ; 127 174: 03 c0 rjmp .+6 ; 0x17c #endif #if defined(TCCR2A) && defined(COM2B1) case TIMER2B: cbi(TCCR2A, COM2B1); break; 176: 80 91 b0 00 lds r24, 0x00B0 17a: 8f 7d andi r24, 0xDF ; 223 17c: 80 93 b0 00 sts 0x00B0, r24 // If the pin that support PWM output, we need to turn it off // before getting a digital reading. if (timer != NOT_ON_TIMER) turnOffPWM(timer); if (*portInputRegister(port) & bit) return HIGH; 180: f0 e0 ldi r31, 0x00 ; 0 182: ee 0f add r30, r30 184: ff 1f adc r31, r31 186: e4 58 subi r30, 0x84 ; 132 188: ff 4f sbci r31, 0xFF ; 255 18a: a5 91 lpm r26, Z+ 18c: b4 91 lpm r27, Z 18e: ec 91 ld r30, X 190: e9 23 and r30, r25 192: 81 e0 ldi r24, 0x01 ; 1 194: 90 e0 ldi r25, 0x00 ; 0 196: 21 f4 brne .+8 ; 0x1a0 198: 80 e0 ldi r24, 0x00 ; 0 19a: 08 95 ret { uint8_t timer = digitalPinToTimer(pin); uint8_t bit = digitalPinToBitMask(pin); uint8_t port = digitalPinToPort(pin); if (port == NOT_A_PIN) return LOW; 19c: 80 e0 ldi r24, 0x00 ; 0 19e: 90 e0 ldi r25, 0x00 ; 0 // before getting a digital reading. if (timer != NOT_ON_TIMER) turnOffPWM(timer); if (*portInputRegister(port) & bit) return HIGH; return LOW; } 1a0: 08 95 ret 000001a2 <_ZN5Print5writeEPKhj>: // Public Methods ////////////////////////////////////////////////////////////// /* default implementation: may be overridden */ size_t Print::write(const uint8_t *buffer, size_t size) { 1a2: cf 92 push r12 1a4: df 92 push r13 1a6: ef 92 push r14 1a8: ff 92 push r15 1aa: 0f 93 push r16 1ac: 1f 93 push r17 1ae: cf 93 push r28 1b0: df 93 push r29 1b2: 6c 01 movw r12, r24 1b4: 7a 01 movw r14, r20 1b6: 8b 01 movw r16, r22 size_t n = 0; 1b8: c0 e0 ldi r28, 0x00 ; 0 1ba: d0 e0 ldi r29, 0x00 ; 0 while (size--) { 1bc: ce 15 cp r28, r14 1be: df 05 cpc r29, r15 1c0: 89 f0 breq .+34 ; 0x1e4 <_ZN5Print5writeEPKhj+0x42> if (write(*buffer++)) n++; 1c2: d8 01 movw r26, r16 1c4: 6d 91 ld r22, X+ 1c6: 8d 01 movw r16, r26 1c8: d6 01 movw r26, r12 1ca: ed 91 ld r30, X+ 1cc: fc 91 ld r31, X 1ce: 01 90 ld r0, Z+ 1d0: f0 81 ld r31, Z 1d2: e0 2d mov r30, r0 1d4: c6 01 movw r24, r12 1d6: 09 95 icall 1d8: 89 2b or r24, r25 1da: 11 f4 brne .+4 ; 0x1e0 <_ZN5Print5writeEPKhj+0x3e> 1dc: 7e 01 movw r14, r28 1de: 02 c0 rjmp .+4 ; 0x1e4 <_ZN5Print5writeEPKhj+0x42> 1e0: 21 96 adiw r28, 0x01 ; 1 1e2: ec cf rjmp .-40 ; 0x1bc <_ZN5Print5writeEPKhj+0x1a> else break; } return n; } 1e4: c7 01 movw r24, r14 1e6: df 91 pop r29 1e8: cf 91 pop r28 1ea: 1f 91 pop r17 1ec: 0f 91 pop r16 1ee: ff 90 pop r15 1f0: ef 90 pop r14 1f2: df 90 pop r13 1f4: cf 90 pop r12 1f6: 08 95 ret 000001f8 <_ZN5Print5flushEv>: size_t println(unsigned long, int = DEC); size_t println(double, int = 2); size_t println(const Printable&); size_t println(void); virtual void flush() { /* Empty implementation for backward compatibility */ } 1f8: 08 95 ret 000001fa <_ZN5Print17availableForWriteEv>: return write((const uint8_t *)buffer, size); } // default to zero, meaning "a single write may block" // should be overriden by subclasses with buffering virtual int availableForWrite() { return 0; } 1fa: 80 e0 ldi r24, 0x00 ; 0 1fc: 90 e0 ldi r25, 0x00 ; 0 1fe: 08 95 ret 00000200 <_ZN14HardwareSerial17availableForWriteEv>: { #if (SERIAL_TX_BUFFER_SIZE>256) uint8_t oldSREG = SREG; cli(); #endif tx_buffer_index_t head = _tx_buffer_head; 200: fc 01 movw r30, r24 202: 53 8d ldd r21, Z+27 ; 0x1b tx_buffer_index_t tail = _tx_buffer_tail; 204: 44 8d ldd r20, Z+28 ; 0x1c 206: 25 2f mov r18, r21 208: 30 e0 ldi r19, 0x00 ; 0 20a: 84 2f mov r24, r20 20c: 90 e0 ldi r25, 0x00 ; 0 #if (SERIAL_TX_BUFFER_SIZE>256) SREG = oldSREG; #endif if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail; 20e: 82 1b sub r24, r18 210: 93 0b sbc r25, r19 212: 54 17 cp r21, r20 214: 10 f0 brcs .+4 ; 0x21a <_ZN14HardwareSerial17availableForWriteEv+0x1a> 216: cf 96 adiw r24, 0x3f ; 63 218: 08 95 ret return tail - head - 1; 21a: 01 97 sbiw r24, 0x01 ; 1 } 21c: 08 95 ret 0000021e <_ZN14HardwareSerial4readEv>: return _rx_buffer[_rx_buffer_tail]; } } int HardwareSerial::read(void) { 21e: fc 01 movw r30, r24 // if the head isn't ahead of the tail, we don't have any characters if (_rx_buffer_head == _rx_buffer_tail) { 220: 91 8d ldd r25, Z+25 ; 0x19 222: 82 8d ldd r24, Z+26 ; 0x1a 224: 98 17 cp r25, r24 226: 61 f0 breq .+24 ; 0x240 <_ZN14HardwareSerial4readEv+0x22> return -1; } else { unsigned char c = _rx_buffer[_rx_buffer_tail]; 228: 82 8d ldd r24, Z+26 ; 0x1a 22a: df 01 movw r26, r30 22c: a8 0f add r26, r24 22e: b1 1d adc r27, r1 230: 5d 96 adiw r26, 0x1d ; 29 232: 8c 91 ld r24, X _rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE; 234: 92 8d ldd r25, Z+26 ; 0x1a 236: 9f 5f subi r25, 0xFF ; 255 238: 9f 73 andi r25, 0x3F ; 63 23a: 92 8f std Z+26, r25 ; 0x1a return c; 23c: 90 e0 ldi r25, 0x00 ; 0 23e: 08 95 ret int HardwareSerial::read(void) { // if the head isn't ahead of the tail, we don't have any characters if (_rx_buffer_head == _rx_buffer_tail) { return -1; 240: 8f ef ldi r24, 0xFF ; 255 242: 9f ef ldi r25, 0xFF ; 255 } else { unsigned char c = _rx_buffer[_rx_buffer_tail]; _rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE; return c; } } 244: 08 95 ret 00000246 <_ZN14HardwareSerial4peekEv>: { return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE; } int HardwareSerial::peek(void) { 246: fc 01 movw r30, r24 if (_rx_buffer_head == _rx_buffer_tail) { 248: 91 8d ldd r25, Z+25 ; 0x19 24a: 82 8d ldd r24, Z+26 ; 0x1a 24c: 98 17 cp r25, r24 24e: 31 f0 breq .+12 ; 0x25c <_ZN14HardwareSerial4peekEv+0x16> return -1; } else { return _rx_buffer[_rx_buffer_tail]; 250: 82 8d ldd r24, Z+26 ; 0x1a 252: e8 0f add r30, r24 254: f1 1d adc r31, r1 256: 85 8d ldd r24, Z+29 ; 0x1d 258: 90 e0 ldi r25, 0x00 ; 0 25a: 08 95 ret } int HardwareSerial::peek(void) { if (_rx_buffer_head == _rx_buffer_tail) { return -1; 25c: 8f ef ldi r24, 0xFF ; 255 25e: 9f ef ldi r25, 0xFF ; 255 } else { return _rx_buffer[_rx_buffer_tail]; } } 260: 08 95 ret 00000262 <_ZN14HardwareSerial9availableEv>: // clear any received data _rx_buffer_head = _rx_buffer_tail; } int HardwareSerial::available(void) { 262: fc 01 movw r30, r24 return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE; 264: 91 8d ldd r25, Z+25 ; 0x19 266: 22 8d ldd r18, Z+26 ; 0x1a 268: 89 2f mov r24, r25 26a: 90 e0 ldi r25, 0x00 ; 0 26c: 80 5c subi r24, 0xC0 ; 192 26e: 9f 4f sbci r25, 0xFF ; 255 270: 82 1b sub r24, r18 272: 91 09 sbc r25, r1 } 274: 8f 73 andi r24, 0x3F ; 63 276: 99 27 eor r25, r25 278: 08 95 ret 0000027a <_Z17Serial0_availablev>: #endif // Function that can be weakly referenced by serialEventRun to prevent // pulling in this file if it's not otherwise used. bool Serial0_available() { return Serial.available(); 27a: 8f e2 ldi r24, 0x2F ; 47 27c: 91 e0 ldi r25, 0x01 ; 1 27e: 0e 94 31 01 call 0x262 ; 0x262 <_ZN14HardwareSerial9availableEv> 282: 21 e0 ldi r18, 0x01 ; 1 284: 89 2b or r24, r25 286: 09 f4 brne .+2 ; 0x28a <_Z17Serial0_availablev+0x10> 288: 20 e0 ldi r18, 0x00 ; 0 } 28a: 82 2f mov r24, r18 28c: 08 95 ret 0000028e <_ZN14HardwareSerial17_tx_udr_empty_irqEv>: } // Actual interrupt handlers ////////////////////////////////////////////////////////////// void HardwareSerial::_tx_udr_empty_irq(void) { 28e: fc 01 movw r30, r24 // If interrupts are enabled, there must be more data in the output // buffer. Send the next byte unsigned char c = _tx_buffer[_tx_buffer_tail]; 290: 84 8d ldd r24, Z+28 ; 0x1c 292: df 01 movw r26, r30 294: a8 0f add r26, r24 296: b1 1d adc r27, r1 298: a3 5a subi r26, 0xA3 ; 163 29a: bf 4f sbci r27, 0xFF ; 255 29c: 2c 91 ld r18, X _tx_buffer_tail = (_tx_buffer_tail + 1) % SERIAL_TX_BUFFER_SIZE; 29e: 84 8d ldd r24, Z+28 ; 0x1c 2a0: 90 e0 ldi r25, 0x00 ; 0 2a2: 01 96 adiw r24, 0x01 ; 1 2a4: 8f 73 andi r24, 0x3F ; 63 2a6: 99 27 eor r25, r25 2a8: 84 8f std Z+28, r24 ; 0x1c *_udr = c; 2aa: a6 89 ldd r26, Z+22 ; 0x16 2ac: b7 89 ldd r27, Z+23 ; 0x17 2ae: 2c 93 st X, r18 // clear the TXC bit -- "can be cleared by writing a one to its bit // location". This makes sure flush() won't return until the bytes // actually got written sbi(*_ucsra, TXC0); 2b0: a0 89 ldd r26, Z+16 ; 0x10 2b2: b1 89 ldd r27, Z+17 ; 0x11 2b4: 8c 91 ld r24, X 2b6: 80 64 ori r24, 0x40 ; 64 2b8: 8c 93 st X, r24 if (_tx_buffer_head == _tx_buffer_tail) { 2ba: 93 8d ldd r25, Z+27 ; 0x1b 2bc: 84 8d ldd r24, Z+28 ; 0x1c 2be: 98 13 cpse r25, r24 2c0: 06 c0 rjmp .+12 ; 0x2ce <_ZN14HardwareSerial17_tx_udr_empty_irqEv+0x40> // Buffer empty, so disable interrupts cbi(*_ucsrb, UDRIE0); 2c2: 02 88 ldd r0, Z+18 ; 0x12 2c4: f3 89 ldd r31, Z+19 ; 0x13 2c6: e0 2d mov r30, r0 2c8: 80 81 ld r24, Z 2ca: 8f 7d andi r24, 0xDF ; 223 2cc: 80 83 st Z, r24 2ce: 08 95 ret 000002d0 <_ZN14HardwareSerial5writeEh>: // If we get here, nothing is queued anymore (DRIE is disabled) and // the hardware finished tranmission (TXC is set). } size_t HardwareSerial::write(uint8_t c) { 2d0: ef 92 push r14 2d2: ff 92 push r15 2d4: 0f 93 push r16 2d6: 1f 93 push r17 2d8: cf 93 push r28 2da: df 93 push r29 2dc: ec 01 movw r28, r24 _written = true; 2de: 81 e0 ldi r24, 0x01 ; 1 2e0: 88 8f std Y+24, r24 ; 0x18 // If the buffer and the data register is empty, just write the byte // to the data register and be done. This shortcut helps // significantly improve the effective datarate at high (> // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { 2e2: 9b 8d ldd r25, Y+27 ; 0x1b 2e4: 8c 8d ldd r24, Y+28 ; 0x1c 2e6: 98 13 cpse r25, r24 2e8: 05 c0 rjmp .+10 ; 0x2f4 <_ZN14HardwareSerial5writeEh+0x24> 2ea: e8 89 ldd r30, Y+16 ; 0x10 2ec: f9 89 ldd r31, Y+17 ; 0x11 2ee: 80 81 ld r24, Z 2f0: 85 fd sbrc r24, 5 2f2: 24 c0 rjmp .+72 ; 0x33c <_ZN14HardwareSerial5writeEh+0x6c> 2f4: f6 2e mov r15, r22 *_udr = c; sbi(*_ucsra, TXC0); return 1; } tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE; 2f6: 0b 8d ldd r16, Y+27 ; 0x1b 2f8: 10 e0 ldi r17, 0x00 ; 0 2fa: 0f 5f subi r16, 0xFF ; 255 2fc: 1f 4f sbci r17, 0xFF ; 255 2fe: 0f 73 andi r16, 0x3F ; 63 300: 11 27 eor r17, r17 302: e0 2e mov r14, r16 // If the output buffer is full, there's nothing for it other than to // wait for the interrupt handler to empty it a bit while (i == _tx_buffer_tail) { 304: 8c 8d ldd r24, Y+28 ; 0x1c 306: e8 12 cpse r14, r24 308: 0c c0 rjmp .+24 ; 0x322 <_ZN14HardwareSerial5writeEh+0x52> if (bit_is_clear(SREG, SREG_I)) { 30a: 0f b6 in r0, 0x3f ; 63 30c: 07 fc sbrc r0, 7 30e: fa cf rjmp .-12 ; 0x304 <_ZN14HardwareSerial5writeEh+0x34> // Interrupts are disabled, so we'll have to poll the data // register empty flag ourselves. If it is set, pretend an // interrupt has happened and call the handler to free up // space for us. if(bit_is_set(*_ucsra, UDRE0)) 310: e8 89 ldd r30, Y+16 ; 0x10 312: f9 89 ldd r31, Y+17 ; 0x11 314: 80 81 ld r24, Z 316: 85 ff sbrs r24, 5 318: f5 cf rjmp .-22 ; 0x304 <_ZN14HardwareSerial5writeEh+0x34> _tx_udr_empty_irq(); 31a: ce 01 movw r24, r28 31c: 0e 94 47 01 call 0x28e ; 0x28e <_ZN14HardwareSerial17_tx_udr_empty_irqEv> 320: f1 cf rjmp .-30 ; 0x304 <_ZN14HardwareSerial5writeEh+0x34> } else { // nop, the interrupt handler will free up space for us } } _tx_buffer[_tx_buffer_head] = c; 322: 8b 8d ldd r24, Y+27 ; 0x1b 324: fe 01 movw r30, r28 326: e8 0f add r30, r24 328: f1 1d adc r31, r1 32a: e3 5a subi r30, 0xA3 ; 163 32c: ff 4f sbci r31, 0xFF ; 255 32e: f0 82 st Z, r15 _tx_buffer_head = i; 330: 0b 8f std Y+27, r16 ; 0x1b sbi(*_ucsrb, UDRIE0); 332: ea 89 ldd r30, Y+18 ; 0x12 334: fb 89 ldd r31, Y+19 ; 0x13 336: 80 81 ld r24, Z 338: 80 62 ori r24, 0x20 ; 32 33a: 07 c0 rjmp .+14 ; 0x34a <_ZN14HardwareSerial5writeEh+0x7a> // If the buffer and the data register is empty, just write the byte // to the data register and be done. This shortcut helps // significantly improve the effective datarate at high (> // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { *_udr = c; 33c: ee 89 ldd r30, Y+22 ; 0x16 33e: ff 89 ldd r31, Y+23 ; 0x17 340: 60 83 st Z, r22 sbi(*_ucsra, TXC0); 342: e8 89 ldd r30, Y+16 ; 0x10 344: f9 89 ldd r31, Y+17 ; 0x11 346: 80 81 ld r24, Z 348: 80 64 ori r24, 0x40 ; 64 34a: 80 83 st Z, r24 _tx_buffer_head = i; sbi(*_ucsrb, UDRIE0); return 1; } 34c: 81 e0 ldi r24, 0x01 ; 1 34e: 90 e0 ldi r25, 0x00 ; 0 350: df 91 pop r29 352: cf 91 pop r28 354: 1f 91 pop r17 356: 0f 91 pop r16 358: ff 90 pop r15 35a: ef 90 pop r14 35c: 08 95 ret 0000035e <_ZN14HardwareSerial5flushEv>: if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail; return tail - head - 1; } void HardwareSerial::flush() { 35e: cf 93 push r28 360: df 93 push r29 362: ec 01 movw r28, r24 // If we have never written a byte, no need to flush. This special // case is needed since there is no way to force the TXC (transmit // complete) bit to 1 during initialization if (!_written) 364: 88 8d ldd r24, Y+24 ; 0x18 366: 88 23 and r24, r24 368: c9 f0 breq .+50 ; 0x39c <_ZN14HardwareSerial5flushEv+0x3e> return; while (bit_is_set(*_ucsrb, UDRIE0) || bit_is_clear(*_ucsra, TXC0)) { 36a: ea 89 ldd r30, Y+18 ; 0x12 36c: fb 89 ldd r31, Y+19 ; 0x13 36e: 80 81 ld r24, Z 370: 85 fd sbrc r24, 5 372: 05 c0 rjmp .+10 ; 0x37e <_ZN14HardwareSerial5flushEv+0x20> 374: a8 89 ldd r26, Y+16 ; 0x10 376: b9 89 ldd r27, Y+17 ; 0x11 378: 8c 91 ld r24, X 37a: 86 fd sbrc r24, 6 37c: 0f c0 rjmp .+30 ; 0x39c <_ZN14HardwareSerial5flushEv+0x3e> if (bit_is_clear(SREG, SREG_I) && bit_is_set(*_ucsrb, UDRIE0)) 37e: 0f b6 in r0, 0x3f ; 63 380: 07 fc sbrc r0, 7 382: f5 cf rjmp .-22 ; 0x36e <_ZN14HardwareSerial5flushEv+0x10> 384: 80 81 ld r24, Z 386: 85 ff sbrs r24, 5 388: f2 cf rjmp .-28 ; 0x36e <_ZN14HardwareSerial5flushEv+0x10> // Interrupts are globally disabled, but the DR empty // interrupt should be enabled, so poll the DR empty flag to // prevent deadlock if (bit_is_set(*_ucsra, UDRE0)) 38a: a8 89 ldd r26, Y+16 ; 0x10 38c: b9 89 ldd r27, Y+17 ; 0x11 38e: 8c 91 ld r24, X 390: 85 ff sbrs r24, 5 392: ed cf rjmp .-38 ; 0x36e <_ZN14HardwareSerial5flushEv+0x10> _tx_udr_empty_irq(); 394: ce 01 movw r24, r28 396: 0e 94 47 01 call 0x28e ; 0x28e <_ZN14HardwareSerial17_tx_udr_empty_irqEv> 39a: e7 cf rjmp .-50 ; 0x36a <_ZN14HardwareSerial5flushEv+0xc> } // If we get here, nothing is queued anymore (DRIE is disabled) and // the hardware finished tranmission (TXC is set). } 39c: df 91 pop r29 39e: cf 91 pop r28 3a0: 08 95 ret 000003a2 <_Z14serialEventRunv>: #endif void serialEventRun(void) { #if defined(HAVE_HWSERIAL0) if (Serial0_available && serialEvent && Serial0_available()) serialEvent(); 3a2: 80 e0 ldi r24, 0x00 ; 0 3a4: 90 e0 ldi r25, 0x00 ; 0 3a6: 89 2b or r24, r25 3a8: 29 f0 breq .+10 ; 0x3b4 <_Z14serialEventRunv+0x12> 3aa: 0e 94 3d 01 call 0x27a ; 0x27a <_Z17Serial0_availablev> 3ae: 81 11 cpse r24, r1 3b0: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 3b4: 08 95 ret 000003b6 : return m; } unsigned long micros() { unsigned long m; uint8_t oldSREG = SREG, t; 3b6: 3f b7 in r19, 0x3f ; 63 cli(); 3b8: f8 94 cli m = timer0_overflow_count; 3ba: 80 91 1f 01 lds r24, 0x011F 3be: 90 91 20 01 lds r25, 0x0120 3c2: a0 91 21 01 lds r26, 0x0121 3c6: b0 91 22 01 lds r27, 0x0122 #if defined(TCNT0) t = TCNT0; 3ca: 26 b5 in r18, 0x26 ; 38 #else #error TIMER 0 not defined #endif #ifdef TIFR0 if ((TIFR0 & _BV(TOV0)) && (t < 255)) 3cc: a8 9b sbis 0x15, 0 ; 21 3ce: 05 c0 rjmp .+10 ; 0x3da 3d0: 2f 3f cpi r18, 0xFF ; 255 3d2: 19 f0 breq .+6 ; 0x3da m++; 3d4: 01 96 adiw r24, 0x01 ; 1 3d6: a1 1d adc r26, r1 3d8: b1 1d adc r27, r1 #else if ((TIFR & _BV(TOV0)) && (t < 255)) m++; #endif SREG = oldSREG; 3da: 3f bf out 0x3f, r19 ; 63 return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond()); 3dc: ba 2f mov r27, r26 3de: a9 2f mov r26, r25 3e0: 98 2f mov r25, r24 3e2: 88 27 eor r24, r24 3e4: 82 0f add r24, r18 3e6: 91 1d adc r25, r1 3e8: a1 1d adc r26, r1 3ea: b1 1d adc r27, r1 3ec: bc 01 movw r22, r24 3ee: cd 01 movw r24, r26 3f0: 42 e0 ldi r20, 0x02 ; 2 3f2: 66 0f add r22, r22 3f4: 77 1f adc r23, r23 3f6: 88 1f adc r24, r24 3f8: 99 1f adc r25, r25 3fa: 4a 95 dec r20 3fc: d1 f7 brne .-12 ; 0x3f2 } 3fe: 08 95 ret 00000400 <_ZN5Print5writeEPKc.constprop.10>: int getWriteError() { return write_error; } void clearWriteError() { setWriteError(0); } virtual size_t write(uint8_t) = 0; size_t write(const char *str) { if (str == NULL) return 0; 400: 00 97 sbiw r24, 0x00 ; 0 402: 69 f0 breq .+26 ; 0x41e <_ZN5Print5writeEPKc.constprop.10+0x1e> return write((const uint8_t *)str, strlen(str)); 404: fc 01 movw r30, r24 406: 01 90 ld r0, Z+ 408: 00 20 and r0, r0 40a: e9 f7 brne .-6 ; 0x406 <_ZN5Print5writeEPKc.constprop.10+0x6> 40c: 31 97 sbiw r30, 0x01 ; 1 40e: af 01 movw r20, r30 410: 48 1b sub r20, r24 412: 59 0b sbc r21, r25 414: bc 01 movw r22, r24 416: 8f e2 ldi r24, 0x2F ; 47 418: 91 e0 ldi r25, 0x01 ; 1 41a: 0c 94 d1 00 jmp 0x1a2 ; 0x1a2 <_ZN5Print5writeEPKhj> } 41e: 80 e0 ldi r24, 0x00 ; 0 420: 90 e0 ldi r25, 0x00 ; 0 422: 08 95 ret 00000424 <__cxa_pure_virtual>: extern "C" void __cxa_deleted_virtual(void) __attribute__ ((__noreturn__)); void __cxa_pure_virtual(void) { // We might want to write some diagnostics to uart in this case //std::terminate(); abort(); 424: 0e 94 50 04 call 0x8a0 ; 0x8a0 00000428 <__vector_19>: #elif defined(USART_UDRE_vect) ISR(USART_UDRE_vect) #else #error "Don't know what the Data Register Empty vector is called for Serial" #endif { 428: 1f 92 push r1 42a: 0f 92 push r0 42c: 0f b6 in r0, 0x3f ; 63 42e: 0f 92 push r0 430: 11 24 eor r1, r1 432: 2f 93 push r18 434: 3f 93 push r19 436: 4f 93 push r20 438: 5f 93 push r21 43a: 6f 93 push r22 43c: 7f 93 push r23 43e: 8f 93 push r24 440: 9f 93 push r25 442: af 93 push r26 444: bf 93 push r27 446: ef 93 push r30 448: ff 93 push r31 Serial._tx_udr_empty_irq(); 44a: 8f e2 ldi r24, 0x2F ; 47 44c: 91 e0 ldi r25, 0x01 ; 1 44e: 0e 94 47 01 call 0x28e ; 0x28e <_ZN14HardwareSerial17_tx_udr_empty_irqEv> } 452: ff 91 pop r31 454: ef 91 pop r30 456: bf 91 pop r27 458: af 91 pop r26 45a: 9f 91 pop r25 45c: 8f 91 pop r24 45e: 7f 91 pop r23 460: 6f 91 pop r22 462: 5f 91 pop r21 464: 4f 91 pop r20 466: 3f 91 pop r19 468: 2f 91 pop r18 46a: 0f 90 pop r0 46c: 0f be out 0x3f, r0 ; 63 46e: 0f 90 pop r0 470: 1f 90 pop r1 472: 18 95 reti 00000474 <__vector_18>: #elif defined(USART_RXC_vect) ISR(USART_RXC_vect) // ATmega8 #else #error "Don't know what the Data Received vector is called for Serial" #endif { 474: 1f 92 push r1 476: 0f 92 push r0 478: 0f b6 in r0, 0x3f ; 63 47a: 0f 92 push r0 47c: 11 24 eor r1, r1 47e: 2f 93 push r18 480: 8f 93 push r24 482: 9f 93 push r25 484: ef 93 push r30 486: ff 93 push r31 // Actual interrupt handlers ////////////////////////////////////////////////////////////// void HardwareSerial::_rx_complete_irq(void) { if (bit_is_clear(*_ucsra, UPE0)) { 488: e0 91 3f 01 lds r30, 0x013F 48c: f0 91 40 01 lds r31, 0x0140 490: 80 81 ld r24, Z 492: e0 91 45 01 lds r30, 0x0145 496: f0 91 46 01 lds r31, 0x0146 49a: 82 fd sbrc r24, 2 49c: 12 c0 rjmp .+36 ; 0x4c2 <__vector_18+0x4e> // No Parity error, read byte and store it in the buffer if there is // room unsigned char c = *_udr; 49e: 90 81 ld r25, Z rx_buffer_index_t i = (unsigned int)(_rx_buffer_head + 1) % SERIAL_RX_BUFFER_SIZE; 4a0: 80 91 48 01 lds r24, 0x0148 4a4: 8f 5f subi r24, 0xFF ; 255 4a6: 8f 73 andi r24, 0x3F ; 63 // if we should be storing the received character into the location // just before the tail (meaning that the head would advance to the // current location of the tail), we're about to overflow the buffer // and so we don't write the character or advance the head. if (i != _rx_buffer_tail) { 4a8: 20 91 49 01 lds r18, 0x0149 4ac: 82 17 cp r24, r18 4ae: 51 f0 breq .+20 ; 0x4c4 <__vector_18+0x50> _rx_buffer[_rx_buffer_head] = c; 4b0: e0 91 48 01 lds r30, 0x0148 4b4: f0 e0 ldi r31, 0x00 ; 0 4b6: e1 5d subi r30, 0xD1 ; 209 4b8: fe 4f sbci r31, 0xFE ; 254 4ba: 95 8f std Z+29, r25 ; 0x1d _rx_buffer_head = i; 4bc: 80 93 48 01 sts 0x0148, r24 4c0: 01 c0 rjmp .+2 ; 0x4c4 <__vector_18+0x50> } } else { // Parity error, read byte but discard it *_udr; 4c2: 80 81 ld r24, Z Serial._rx_complete_irq(); } 4c4: ff 91 pop r31 4c6: ef 91 pop r30 4c8: 9f 91 pop r25 4ca: 8f 91 pop r24 4cc: 2f 91 pop r18 4ce: 0f 90 pop r0 4d0: 0f be out 0x3f, r0 ; 63 4d2: 0f 90 pop r0 4d4: 1f 90 pop r1 4d6: 18 95 reti 000004d8 <__vector_16>: #if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ISR(TIM0_OVF_vect) #else ISR(TIMER0_OVF_vect) #endif { 4d8: 1f 92 push r1 4da: 0f 92 push r0 4dc: 0f b6 in r0, 0x3f ; 63 4de: 0f 92 push r0 4e0: 11 24 eor r1, r1 4e2: 2f 93 push r18 4e4: 3f 93 push r19 4e6: 8f 93 push r24 4e8: 9f 93 push r25 4ea: af 93 push r26 4ec: bf 93 push r27 // copy these to local variables so they can be stored in registers // (volatile variables must be read from memory on every access) unsigned long m = timer0_millis; 4ee: 80 91 1b 01 lds r24, 0x011B 4f2: 90 91 1c 01 lds r25, 0x011C 4f6: a0 91 1d 01 lds r26, 0x011D 4fa: b0 91 1e 01 lds r27, 0x011E unsigned char f = timer0_fract; 4fe: 30 91 1a 01 lds r19, 0x011A m += MILLIS_INC; f += FRACT_INC; 502: 23 e0 ldi r18, 0x03 ; 3 504: 23 0f add r18, r19 if (f >= FRACT_MAX) { 506: 2d 37 cpi r18, 0x7D ; 125 508: 20 f4 brcc .+8 ; 0x512 <__vector_16+0x3a> // copy these to local variables so they can be stored in registers // (volatile variables must be read from memory on every access) unsigned long m = timer0_millis; unsigned char f = timer0_fract; m += MILLIS_INC; 50a: 01 96 adiw r24, 0x01 ; 1 50c: a1 1d adc r26, r1 50e: b1 1d adc r27, r1 510: 05 c0 rjmp .+10 ; 0x51c <__vector_16+0x44> f += FRACT_INC; if (f >= FRACT_MAX) { f -= FRACT_MAX; 512: 26 e8 ldi r18, 0x86 ; 134 514: 23 0f add r18, r19 m += 1; 516: 02 96 adiw r24, 0x02 ; 2 518: a1 1d adc r26, r1 51a: b1 1d adc r27, r1 } timer0_fract = f; 51c: 20 93 1a 01 sts 0x011A, r18 timer0_millis = m; 520: 80 93 1b 01 sts 0x011B, r24 524: 90 93 1c 01 sts 0x011C, r25 528: a0 93 1d 01 sts 0x011D, r26 52c: b0 93 1e 01 sts 0x011E, r27 timer0_overflow_count++; 530: 80 91 1f 01 lds r24, 0x011F 534: 90 91 20 01 lds r25, 0x0120 538: a0 91 21 01 lds r26, 0x0121 53c: b0 91 22 01 lds r27, 0x0122 540: 01 96 adiw r24, 0x01 ; 1 542: a1 1d adc r26, r1 544: b1 1d adc r27, r1 546: 80 93 1f 01 sts 0x011F, r24 54a: 90 93 20 01 sts 0x0120, r25 54e: a0 93 21 01 sts 0x0121, r26 552: b0 93 22 01 sts 0x0122, r27 } 556: bf 91 pop r27 558: af 91 pop r26 55a: 9f 91 pop r25 55c: 8f 91 pop r24 55e: 3f 91 pop r19 560: 2f 91 pop r18 562: 0f 90 pop r0 564: 0f be out 0x3f, r0 ; 63 566: 0f 90 pop r0 568: 1f 90 pop r1 56a: 18 95 reti 0000056c
: void setupUSB() __attribute__((weak)); void setupUSB() { } int main(void) { 56c: cf 93 push r28 56e: df 93 push r29 570: cd b7 in r28, 0x3d ; 61 572: de b7 in r29, 0x3e ; 62 574: a1 97 sbiw r28, 0x21 ; 33 576: 0f b6 in r0, 0x3f ; 63 578: f8 94 cli 57a: de bf out 0x3e, r29 ; 62 57c: 0f be out 0x3f, r0 ; 63 57e: cd bf out 0x3d, r28 ; 61 void init() { // this needs to be called before setup() or some functions won't // work there sei(); 580: 78 94 sei // on the ATmega168, timer 0 is also used for fast hardware pwm // (using phase-correct PWM would mean that timer 0 overflowed half as often // resulting in different millis() behavior on the ATmega8 and ATmega168) #if defined(TCCR0A) && defined(WGM01) sbi(TCCR0A, WGM01); 582: 84 b5 in r24, 0x24 ; 36 584: 82 60 ori r24, 0x02 ; 2 586: 84 bd out 0x24, r24 ; 36 sbi(TCCR0A, WGM00); 588: 84 b5 in r24, 0x24 ; 36 58a: 81 60 ori r24, 0x01 ; 1 58c: 84 bd out 0x24, r24 ; 36 // this combination is for the standard atmega8 sbi(TCCR0, CS01); sbi(TCCR0, CS00); #elif defined(TCCR0B) && defined(CS01) && defined(CS00) // this combination is for the standard 168/328/1280/2560 sbi(TCCR0B, CS01); 58e: 85 b5 in r24, 0x25 ; 37 590: 82 60 ori r24, 0x02 ; 2 592: 85 bd out 0x25, r24 ; 37 sbi(TCCR0B, CS00); 594: 85 b5 in r24, 0x25 ; 37 596: 81 60 ori r24, 0x01 ; 1 598: 85 bd out 0x25, r24 ; 37 // enable timer 0 overflow interrupt #if defined(TIMSK) && defined(TOIE0) sbi(TIMSK, TOIE0); #elif defined(TIMSK0) && defined(TOIE0) sbi(TIMSK0, TOIE0); 59a: 80 91 6e 00 lds r24, 0x006E 59e: 81 60 ori r24, 0x01 ; 1 5a0: 80 93 6e 00 sts 0x006E, r24 // this is better for motors as it ensures an even waveform // note, however, that fast pwm mode can achieve a frequency of up // 8 MHz (with a 16 MHz clock) at 50% duty cycle #if defined(TCCR1B) && defined(CS11) && defined(CS10) TCCR1B = 0; 5a4: 10 92 81 00 sts 0x0081, r1 // set timer 1 prescale factor to 64 sbi(TCCR1B, CS11); 5a8: 80 91 81 00 lds r24, 0x0081 5ac: 82 60 ori r24, 0x02 ; 2 5ae: 80 93 81 00 sts 0x0081, r24 #if F_CPU >= 8000000L sbi(TCCR1B, CS10); 5b2: 80 91 81 00 lds r24, 0x0081 5b6: 81 60 ori r24, 0x01 ; 1 5b8: 80 93 81 00 sts 0x0081, r24 sbi(TCCR1, CS10); #endif #endif // put timer 1 in 8-bit phase correct pwm mode #if defined(TCCR1A) && defined(WGM10) sbi(TCCR1A, WGM10); 5bc: 80 91 80 00 lds r24, 0x0080 5c0: 81 60 ori r24, 0x01 ; 1 5c2: 80 93 80 00 sts 0x0080, r24 // set timer 2 prescale factor to 64 #if defined(TCCR2) && defined(CS22) sbi(TCCR2, CS22); #elif defined(TCCR2B) && defined(CS22) sbi(TCCR2B, CS22); 5c6: 80 91 b1 00 lds r24, 0x00B1 5ca: 84 60 ori r24, 0x04 ; 4 5cc: 80 93 b1 00 sts 0x00B1, r24 // configure timer 2 for phase correct pwm (8-bit) #if defined(TCCR2) && defined(WGM20) sbi(TCCR2, WGM20); #elif defined(TCCR2A) && defined(WGM20) sbi(TCCR2A, WGM20); 5d0: 80 91 b0 00 lds r24, 0x00B0 5d4: 81 60 ori r24, 0x01 ; 1 5d6: 80 93 b0 00 sts 0x00B0, r24 #endif #if defined(ADCSRA) // set a2d prescaler so we are inside the desired 50-200 KHz range. #if F_CPU >= 16000000 // 16 MHz / 128 = 125 KHz sbi(ADCSRA, ADPS2); 5da: 80 91 7a 00 lds r24, 0x007A 5de: 84 60 ori r24, 0x04 ; 4 5e0: 80 93 7a 00 sts 0x007A, r24 sbi(ADCSRA, ADPS1); 5e4: 80 91 7a 00 lds r24, 0x007A 5e8: 82 60 ori r24, 0x02 ; 2 5ea: 80 93 7a 00 sts 0x007A, r24 sbi(ADCSRA, ADPS0); 5ee: 80 91 7a 00 lds r24, 0x007A 5f2: 81 60 ori r24, 0x01 ; 1 5f4: 80 93 7a 00 sts 0x007A, r24 cbi(ADCSRA, ADPS2); cbi(ADCSRA, ADPS1); sbi(ADCSRA, ADPS0); #endif // enable a2d conversions sbi(ADCSRA, ADEN); 5f8: 80 91 7a 00 lds r24, 0x007A 5fc: 80 68 ori r24, 0x80 ; 128 5fe: 80 93 7a 00 sts 0x007A, r24 // here so they can be used as normal digital i/o; they will be // reconnected in Serial.begin() #if defined(UCSRB) UCSRB = 0; #elif defined(UCSR0B) UCSR0B = 0; 602: 10 92 c1 00 sts 0x00C1, r1 #include "wiring_private.h" #include "pins_arduino.h" void pinMode(uint8_t pin, uint8_t mode) { uint8_t bit = digitalPinToBitMask(pin); 606: ec e9 ldi r30, 0x9C ; 156 608: f0 e0 ldi r31, 0x00 ; 0 60a: 24 91 lpm r18, Z uint8_t port = digitalPinToPort(pin); 60c: e8 e8 ldi r30, 0x88 ; 136 60e: f0 e0 ldi r31, 0x00 ; 0 610: 84 91 lpm r24, Z volatile uint8_t *reg, *out; if (port == NOT_A_PIN) return; 612: 88 23 and r24, r24 614: c9 f0 breq .+50 ; 0x648 // JWS: can I let the optimizer do this? reg = portModeRegister(port); 616: 90 e0 ldi r25, 0x00 ; 0 618: 88 0f add r24, r24 61a: 99 1f adc r25, r25 61c: fc 01 movw r30, r24 61e: ee 58 subi r30, 0x8E ; 142 620: ff 4f sbci r31, 0xFF ; 255 622: 45 91 lpm r20, Z+ 624: 54 91 lpm r21, Z out = portOutputRegister(port); 626: fc 01 movw r30, r24 628: e8 59 subi r30, 0x98 ; 152 62a: ff 4f sbci r31, 0xFF ; 255 62c: a5 91 lpm r26, Z+ 62e: b4 91 lpm r27, Z if (mode == INPUT) { uint8_t oldSREG = SREG; 630: 9f b7 in r25, 0x3f ; 63 cli(); 632: f8 94 cli *reg &= ~bit; 634: fa 01 movw r30, r20 636: 80 81 ld r24, Z 638: 20 95 com r18 63a: 82 23 and r24, r18 63c: 80 83 st Z, r24 *out &= ~bit; 63e: 8c 91 ld r24, X 640: e2 2f mov r30, r18 642: e8 23 and r30, r24 644: ec 93 st X, r30 SREG = oldSREG; 646: 9f bf out 0x3f, r25 ; 63 void HardwareSerial::begin(unsigned long baud, byte config) { // Try u2x mode first uint16_t baud_setting = (F_CPU / 4 / baud - 1) / 2; *_ucsra = 1 << U2X0; 648: e0 91 3f 01 lds r30, 0x013F 64c: f0 91 40 01 lds r31, 0x0140 650: 82 e0 ldi r24, 0x02 ; 2 652: 80 83 st Z, r24 *_ucsra = 0; baud_setting = (F_CPU / 8 / baud - 1) / 2; } // assign the baud_setting, a.k.a. ubrr (USART Baud Rate Register) *_ubrrh = baud_setting >> 8; 654: e0 91 3b 01 lds r30, 0x013B 658: f0 91 3c 01 lds r31, 0x013C 65c: 10 82 st Z, r1 *_ubrrl = baud_setting; 65e: e0 91 3d 01 lds r30, 0x013D 662: f0 91 3e 01 lds r31, 0x013E 666: 8f ec ldi r24, 0xCF ; 207 668: 80 83 st Z, r24 _written = false; 66a: 10 92 47 01 sts 0x0147, r1 //set the data bits, parity, and stop bits #if defined(__AVR_ATmega8__) config |= 0x80; // select UCSRC register (shared with UBRRH) #endif *_ucsrc = config; 66e: e0 91 43 01 lds r30, 0x0143 672: f0 91 44 01 lds r31, 0x0144 676: 86 e0 ldi r24, 0x06 ; 6 678: 80 83 st Z, r24 sbi(*_ucsrb, RXEN0); 67a: e0 91 41 01 lds r30, 0x0141 67e: f0 91 42 01 lds r31, 0x0142 682: 80 81 ld r24, Z 684: 80 61 ori r24, 0x10 ; 16 686: 80 83 st Z, r24 sbi(*_ucsrb, TXEN0); 688: e0 91 41 01 lds r30, 0x0141 68c: f0 91 42 01 lds r31, 0x0142 690: 80 81 ld r24, Z 692: 88 60 ori r24, 0x08 ; 8 694: 80 83 st Z, r24 sbi(*_ucsrb, RXCIE0); 696: e0 91 41 01 lds r30, 0x0141 69a: f0 91 42 01 lds r31, 0x0142 69e: 80 81 ld r24, Z 6a0: 80 68 ori r24, 0x80 ; 128 6a2: 80 83 st Z, r24 cbi(*_ucsrb, UDRIE0); 6a4: e0 91 41 01 lds r30, 0x0141 6a8: f0 91 42 01 lds r31, 0x0142 6ac: 80 81 ld r24, Z 6ae: 8f 7d andi r24, 0xDF ; 223 6b0: 80 83 st Z, r24 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; 6b2: 9a e0 ldi r25, 0x0A ; 10 6b4: 89 2e mov r8, r25 6b6: 91 2c mov r9, r1 6b8: a1 2c mov r10, r1 6ba: b1 2c mov r11, r1 // initialize serial communication: Serial.begin(9600); } void loop() { while(digitalRead(pingPin)==LOW){ 6bc: 0e 94 8c 00 call 0x118 ; 0x118 6c0: 89 2b or r24, r25 6c2: e1 f3 breq .-8 ; 0x6bc } starttime=micros(); 6c4: 0e 94 db 01 call 0x3b6 ; 0x3b6 6c8: 2b 01 movw r4, r22 6ca: 3c 01 movw r6, r24 6cc: 60 93 2b 01 sts 0x012B, r22 6d0: 70 93 2c 01 sts 0x012C, r23 6d4: 80 93 2d 01 sts 0x012D, r24 6d8: 90 93 2e 01 sts 0x012E, r25 while(digitalRead(pingPin)==HIGH){ 6dc: 0e 94 8c 00 call 0x118 ; 0x118 6e0: 01 97 sbiw r24, 0x01 ; 1 6e2: e1 f3 breq .-8 ; 0x6dc } endtime=micros(); 6e4: 0e 94 db 01 call 0x3b6 ; 0x3b6 6e8: 60 93 27 01 sts 0x0127, r22 6ec: 70 93 28 01 sts 0x0128, r23 6f0: 80 93 29 01 sts 0x0129, r24 6f4: 90 93 2a 01 sts 0x012A, r25 duration=endtime-starttime; 6f8: 6b 01 movw r12, r22 6fa: 7c 01 movw r14, r24 6fc: c4 18 sub r12, r4 6fe: d5 08 sbc r13, r5 700: e6 08 sbc r14, r6 702: f7 08 sbc r15, r7 704: c0 92 23 01 sts 0x0123, r12 708: d0 92 24 01 sts 0x0124, r13 70c: e0 92 25 01 sts 0x0125, r14 710: f0 92 26 01 sts 0x0126, r15 size_t Print::print(long n, int base) { if (base == 0) { return write(n); } else if (base == 10) { if (n < 0) { 714: f7 fe sbrs r15, 7 716: 26 c0 rjmp .+76 ; 0x764 return write(str); } size_t Print::print(char c) { return write(c); 718: e0 91 2f 01 lds r30, 0x012F 71c: f0 91 30 01 lds r31, 0x0130 720: 01 90 ld r0, Z+ 722: f0 81 ld r31, Z 724: e0 2d mov r30, r0 726: 6d e2 ldi r22, 0x2D ; 45 728: 8f e2 ldi r24, 0x2F ; 47 72a: 91 e0 ldi r25, 0x01 ; 1 72c: 09 95 icall if (base == 0) { return write(n); } else if (base == 10) { if (n < 0) { int t = print('-'); n = -n; 72e: 22 27 eor r18, r18 730: 33 27 eor r19, r19 732: a9 01 movw r20, r18 734: 2c 19 sub r18, r12 736: 3d 09 sbc r19, r13 738: 4e 09 sbc r20, r14 73a: 5f 09 sbc r21, r15 size_t Print::printNumber(unsigned long n, uint8_t base) { char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. char *str = &buf[sizeof(buf) - 1]; *str = '\0'; 73c: 19 a2 std Y+33, r1 ; 0x21 73e: 8e 01 movw r16, r28 740: 0f 5d subi r16, 0xDF ; 223 742: 1f 4f sbci r17, 0xFF ; 255 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; n /= base; 744: ca 01 movw r24, r20 746: b9 01 movw r22, r18 748: a5 01 movw r20, r10 74a: 94 01 movw r18, r8 74c: 0e 94 28 04 call 0x850 ; 0x850 <__udivmodsi4> *--str = c < 10 ? c + '0' : c + 'A' - 10; 750: 60 5d subi r22, 0xD0 ; 208 752: f8 01 movw r30, r16 754: 62 93 st -Z, r22 756: 8f 01 movw r16, r30 *str = '\0'; // prevent crash if called with base == 1 if (base < 2) base = 10; do { 758: 21 15 cp r18, r1 75a: 31 05 cpc r19, r1 75c: 41 05 cpc r20, r1 75e: 51 05 cpc r21, r1 760: 89 f7 brne .-30 ; 0x744 762: 15 c0 rjmp .+42 ; 0x78e if (n < 0) { int t = print('-'); n = -n; return printNumber(n, 10) + t; } return printNumber(n, 10); 764: a7 01 movw r20, r14 766: 96 01 movw r18, r12 size_t Print::printNumber(unsigned long n, uint8_t base) { char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. char *str = &buf[sizeof(buf) - 1]; *str = '\0'; 768: 19 a2 std Y+33, r1 ; 0x21 76a: 8e 01 movw r16, r28 76c: 0f 5d subi r16, 0xDF ; 223 76e: 1f 4f sbci r17, 0xFF ; 255 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; n /= base; 770: ca 01 movw r24, r20 772: b9 01 movw r22, r18 774: a5 01 movw r20, r10 776: 94 01 movw r18, r8 778: 0e 94 28 04 call 0x850 ; 0x850 <__udivmodsi4> *--str = c < 10 ? c + '0' : c + 'A' - 10; 77c: 60 5d subi r22, 0xD0 ; 208 77e: f8 01 movw r30, r16 780: 62 93 st -Z, r22 782: 8f 01 movw r16, r30 *str = '\0'; // prevent crash if called with base == 1 if (base < 2) base = 10; do { 784: 21 15 cp r18, r1 786: 31 05 cpc r19, r1 788: 41 05 cpc r20, r1 78a: 51 05 cpc r21, r1 78c: 89 f7 brne .-30 ; 0x770 n /= base; *--str = c < 10 ? c + '0' : c + 'A' - 10; } while(n); return write(str); 78e: c8 01 movw r24, r16 790: 0e 94 00 02 call 0x400 ; 0x400 <_ZN5Print5writeEPKc.constprop.10> return write(s.c_str(), s.length()); } size_t Print::print(const char str[]) { return write(str); 794: 82 e1 ldi r24, 0x12 ; 18 796: 91 e0 ldi r25, 0x01 ; 1 798: 0e 94 00 02 call 0x400 ; 0x400 <_ZN5Print5writeEPKc.constprop.10> return x.printTo(*this); } size_t Print::println(void) { return write("\r\n"); 79c: 86 e1 ldi r24, 0x16 ; 22 79e: 91 e0 ldi r25, 0x01 ; 1 7a0: 0e 94 00 02 call 0x400 ; 0x400 <_ZN5Print5writeEPKc.constprop.10> return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond()); } void delay(unsigned long ms) { uint32_t start = micros(); 7a4: 0e 94 db 01 call 0x3b6 ; 0x3b6 7a8: 2b 01 movw r4, r22 7aa: 3c 01 movw r6, r24 7ac: 84 e6 ldi r24, 0x64 ; 100 7ae: c8 2e mov r12, r24 7b0: d1 2c mov r13, r1 7b2: e1 2c mov r14, r1 7b4: f1 2c mov r15, r1 while (ms > 0) { yield(); while ( ms > 0 && (micros() - start) >= 1000) { 7b6: 0e 94 db 01 call 0x3b6 ; 0x3b6 7ba: dc 01 movw r26, r24 7bc: cb 01 movw r24, r22 7be: 84 19 sub r24, r4 7c0: 95 09 sbc r25, r5 7c2: a6 09 sbc r26, r6 7c4: b7 09 sbc r27, r7 7c6: 88 3e cpi r24, 0xE8 ; 232 7c8: 93 40 sbci r25, 0x03 ; 3 7ca: a1 05 cpc r26, r1 7cc: b1 05 cpc r27, r1 7ce: 58 f0 brcs .+22 ; 0x7e6 ms--; 7d0: f1 e0 ldi r31, 0x01 ; 1 7d2: cf 1a sub r12, r31 7d4: d1 08 sbc r13, r1 7d6: e1 08 sbc r14, r1 7d8: f1 08 sbc r15, r1 start += 1000; 7da: 28 ee ldi r18, 0xE8 ; 232 7dc: 42 0e add r4, r18 7de: 23 e0 ldi r18, 0x03 ; 3 7e0: 52 1e adc r5, r18 7e2: 61 1c adc r6, r1 7e4: 71 1c adc r7, r1 { uint32_t start = micros(); while (ms > 0) { yield(); while ( ms > 0 && (micros() - start) >= 1000) { 7e6: c1 14 cp r12, r1 7e8: d1 04 cpc r13, r1 7ea: e1 04 cpc r14, r1 7ec: f1 04 cpc r15, r1 7ee: 19 f7 brne .-58 ; 0x7b6 setup(); for (;;) { loop(); if (serialEventRun) serialEventRun(); 7f0: 0e 94 d1 01 call 0x3a2 ; 0x3a2 <_Z14serialEventRunv> 7f4: 63 cf rjmp .-314 ; 0x6bc 000007f6 <_GLOBAL__sub_I___vector_18>: size_t printNumber(unsigned long, uint8_t); size_t printFloat(double, uint8_t); protected: void setWriteError(int err = 1) { write_error = err; } public: Print() : write_error(0) {} 7f6: ef e2 ldi r30, 0x2F ; 47 7f8: f1 e0 ldi r31, 0x01 ; 1 7fa: 13 82 std Z+3, r1 ; 0x03 7fc: 12 82 std Z+2, r1 ; 0x02 public: virtual int available() = 0; virtual int read() = 0; virtual int peek() = 0; Stream() {_timeout=1000;} 7fe: 88 ee ldi r24, 0xE8 ; 232 800: 93 e0 ldi r25, 0x03 ; 3 802: a0 e0 ldi r26, 0x00 ; 0 804: b0 e0 ldi r27, 0x00 ; 0 806: 84 83 std Z+4, r24 ; 0x04 808: 95 83 std Z+5, r25 ; 0x05 80a: a6 83 std Z+6, r26 ; 0x06 80c: b7 83 std Z+7, r27 ; 0x07 volatile uint8_t *ucsrc, volatile uint8_t *udr) : _ubrrh(ubrrh), _ubrrl(ubrrl), _ucsra(ucsra), _ucsrb(ucsrb), _ucsrc(ucsrc), _udr(udr), _rx_buffer_head(0), _rx_buffer_tail(0), _tx_buffer_head(0), _tx_buffer_tail(0) 80e: 84 e0 ldi r24, 0x04 ; 4 810: 91 e0 ldi r25, 0x01 ; 1 812: 91 83 std Z+1, r25 ; 0x01 814: 80 83 st Z, r24 816: 85 ec ldi r24, 0xC5 ; 197 818: 90 e0 ldi r25, 0x00 ; 0 81a: 95 87 std Z+13, r25 ; 0x0d 81c: 84 87 std Z+12, r24 ; 0x0c 81e: 84 ec ldi r24, 0xC4 ; 196 820: 90 e0 ldi r25, 0x00 ; 0 822: 97 87 std Z+15, r25 ; 0x0f 824: 86 87 std Z+14, r24 ; 0x0e 826: 80 ec ldi r24, 0xC0 ; 192 828: 90 e0 ldi r25, 0x00 ; 0 82a: 91 8b std Z+17, r25 ; 0x11 82c: 80 8b std Z+16, r24 ; 0x10 82e: 81 ec ldi r24, 0xC1 ; 193 830: 90 e0 ldi r25, 0x00 ; 0 832: 93 8b std Z+19, r25 ; 0x13 834: 82 8b std Z+18, r24 ; 0x12 836: 82 ec ldi r24, 0xC2 ; 194 838: 90 e0 ldi r25, 0x00 ; 0 83a: 95 8b std Z+21, r25 ; 0x15 83c: 84 8b std Z+20, r24 ; 0x14 83e: 86 ec ldi r24, 0xC6 ; 198 840: 90 e0 ldi r25, 0x00 ; 0 842: 97 8b std Z+23, r25 ; 0x17 844: 86 8b std Z+22, r24 ; 0x16 846: 11 8e std Z+25, r1 ; 0x19 848: 12 8e std Z+26, r1 ; 0x1a 84a: 13 8e std Z+27, r1 ; 0x1b 84c: 14 8e std Z+28, r1 ; 0x1c 84e: 08 95 ret 00000850 <__udivmodsi4>: 850: a1 e2 ldi r26, 0x21 ; 33 852: 1a 2e mov r1, r26 854: aa 1b sub r26, r26 856: bb 1b sub r27, r27 858: fd 01 movw r30, r26 85a: 0d c0 rjmp .+26 ; 0x876 <__udivmodsi4_ep> 0000085c <__udivmodsi4_loop>: 85c: aa 1f adc r26, r26 85e: bb 1f adc r27, r27 860: ee 1f adc r30, r30 862: ff 1f adc r31, r31 864: a2 17 cp r26, r18 866: b3 07 cpc r27, r19 868: e4 07 cpc r30, r20 86a: f5 07 cpc r31, r21 86c: 20 f0 brcs .+8 ; 0x876 <__udivmodsi4_ep> 86e: a2 1b sub r26, r18 870: b3 0b sbc r27, r19 872: e4 0b sbc r30, r20 874: f5 0b sbc r31, r21 00000876 <__udivmodsi4_ep>: 876: 66 1f adc r22, r22 878: 77 1f adc r23, r23 87a: 88 1f adc r24, r24 87c: 99 1f adc r25, r25 87e: 1a 94 dec r1 880: 69 f7 brne .-38 ; 0x85c <__udivmodsi4_loop> 882: 60 95 com r22 884: 70 95 com r23 886: 80 95 com r24 888: 90 95 com r25 88a: 9b 01 movw r18, r22 88c: ac 01 movw r20, r24 88e: bd 01 movw r22, r26 890: cf 01 movw r24, r30 892: 08 95 ret 00000894 <__tablejump2__>: 894: ee 0f add r30, r30 896: ff 1f adc r31, r31 898: 05 90 lpm r0, Z+ 89a: f4 91 lpm r31, Z 89c: e0 2d mov r30, r0 89e: 09 94 ijmp 000008a0 : 8a0: 81 e0 ldi r24, 0x01 ; 1 8a2: 90 e0 ldi r25, 0x00 ; 0 8a4: f8 94 cli 8a6: 0c 94 55 04 jmp 0x8aa ; 0x8aa <_exit> 000008aa <_exit>: 8aa: f8 94 cli 000008ac <__stop_program>: 8ac: ff cf rjmp .-2 ; 0x8ac <__stop_program>