PulseWidthIntLL.ino.elf: file format elf32-avr Disassembly of section .text: 00000000 <__vectors>: 0: 0c 94 53 00 jmp 0xa6 ; 0xa6 <__ctors_end> 4: 0c 94 62 02 jmp 0x4c4 ; 0x4c4 <__vector_1> 8: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> c: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 10: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 14: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 18: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 1c: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 20: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 24: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 28: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 2c: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 30: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 34: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 38: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 3c: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 40: 0c 94 18 02 jmp 0x430 ; 0x430 <__vector_16> 44: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 48: 0c 94 e6 01 jmp 0x3cc ; 0x3cc <__vector_18> 4c: 0c 94 c0 01 jmp 0x380 ; 0x380 <__vector_19> 50: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 54: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 58: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 5c: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 60: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 64: 0c 94 7b 00 jmp 0xf6 ; 0xf6 <__bad_interrupt> 00000068 <__trampolines_end>: 68: 00 00 nop 6a: 00 00 nop 6c: 25 00 .word 0x0025 ; ???? 6e: 28 00 .word 0x0028 ; ???? 70: 2b 00 .word 0x002b ; ???? 00000072 : 72: 00 00 00 00 24 00 27 00 2a 00 ....$.'.*. 0000007c : 7c: 04 04 04 04 04 04 04 04 02 02 02 02 02 02 03 03 ................ 8c: 03 03 03 03 .... 00000090 : 90: 01 02 04 08 10 20 40 80 01 02 04 08 10 20 01 02 ..... @...... .. a0: 04 08 10 20 ... 000000a4 <__ctors_start>: a4: ef 03 fmulsu r22, r23 000000a6 <__ctors_end>: a6: 11 24 eor r1, r1 a8: 1f be out 0x3f, r1 ; 63 aa: cf ef ldi r28, 0xFF ; 255 ac: d8 e0 ldi r29, 0x08 ; 8 ae: de bf out 0x3e, r29 ; 62 b0: cd bf out 0x3d, r28 ; 61 000000b2 <__do_copy_data>: b2: 11 e0 ldi r17, 0x01 ; 1 b4: a0 e0 ldi r26, 0x00 ; 0 b6: b1 e0 ldi r27, 0x01 ; 1 b8: e6 e9 ldi r30, 0x96 ; 150 ba: f8 e0 ldi r31, 0x08 ; 8 bc: 02 c0 rjmp .+4 ; 0xc2 <__do_copy_data+0x10> be: 05 90 lpm r0, Z+ c0: 0d 92 st X+, r0 c2: aa 31 cpi r26, 0x1A ; 26 c4: b1 07 cpc r27, r17 c6: d9 f7 brne .-10 ; 0xbe <__do_copy_data+0xc> 000000c8 <__do_clear_bss>: c8: 21 e0 ldi r18, 0x01 ; 1 ca: aa e1 ldi r26, 0x1A ; 26 cc: b1 e0 ldi r27, 0x01 ; 1 ce: 01 c0 rjmp .+2 ; 0xd2 <.do_clear_bss_start> 000000d0 <.do_clear_bss_loop>: d0: 1d 92 st X+, r1 000000d2 <.do_clear_bss_start>: d2: ad 3c cpi r26, 0xCD ; 205 d4: b2 07 cpc r27, r18 d6: e1 f7 brne .-8 ; 0xd0 <.do_clear_bss_loop> 000000d8 <__do_global_ctors>: d8: 10 e0 ldi r17, 0x00 ; 0 da: c3 e5 ldi r28, 0x53 ; 83 dc: d0 e0 ldi r29, 0x00 ; 0 de: 04 c0 rjmp .+8 ; 0xe8 <__do_global_ctors+0x10> e0: 21 97 sbiw r28, 0x01 ; 1 e2: fe 01 movw r30, r28 e4: 0e 94 3e 04 call 0x87c ; 0x87c <__tablejump2__> e8: c2 35 cpi r28, 0x52 ; 82 ea: d1 07 cpc r29, r17 ec: c9 f7 brne .-14 ; 0xe0 <__do_global_ctors+0x8> ee: 0e 94 bf 02 call 0x57e ; 0x57e
f2: 0c 94 49 04 jmp 0x892 ; 0x892 <_exit> 000000f6 <__bad_interrupt>: f6: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 000000fa <_ZN5Print5writeEPKhj>: // Public Methods ////////////////////////////////////////////////////////////// /* default implementation: may be overridden */ size_t Print::write(const uint8_t *buffer, size_t size) { fa: cf 92 push r12 fc: df 92 push r13 fe: ef 92 push r14 100: ff 92 push r15 102: 0f 93 push r16 104: 1f 93 push r17 106: cf 93 push r28 108: df 93 push r29 10a: 6c 01 movw r12, r24 10c: 7a 01 movw r14, r20 10e: 8b 01 movw r16, r22 size_t n = 0; 110: c0 e0 ldi r28, 0x00 ; 0 112: d0 e0 ldi r29, 0x00 ; 0 while (size--) { 114: ce 15 cp r28, r14 116: df 05 cpc r29, r15 118: 89 f0 breq .+34 ; 0x13c <_ZN5Print5writeEPKhj+0x42> if (write(*buffer++)) n++; 11a: d8 01 movw r26, r16 11c: 6d 91 ld r22, X+ 11e: 8d 01 movw r16, r26 120: d6 01 movw r26, r12 122: ed 91 ld r30, X+ 124: fc 91 ld r31, X 126: 01 90 ld r0, Z+ 128: f0 81 ld r31, Z 12a: e0 2d mov r30, r0 12c: c6 01 movw r24, r12 12e: 09 95 icall 130: 89 2b or r24, r25 132: 11 f4 brne .+4 ; 0x138 <_ZN5Print5writeEPKhj+0x3e> 134: 7e 01 movw r14, r28 136: 02 c0 rjmp .+4 ; 0x13c <_ZN5Print5writeEPKhj+0x42> 138: 21 96 adiw r28, 0x01 ; 1 13a: ec cf rjmp .-40 ; 0x114 <_ZN5Print5writeEPKhj+0x1a> else break; } return n; } 13c: c7 01 movw r24, r14 13e: df 91 pop r29 140: cf 91 pop r28 142: 1f 91 pop r17 144: 0f 91 pop r16 146: ff 90 pop r15 148: ef 90 pop r14 14a: df 90 pop r13 14c: cf 90 pop r12 14e: 08 95 ret 00000150 <_ZN5Print5flushEv>: size_t println(unsigned long, int = DEC); size_t println(double, int = 2); size_t println(const Printable&); size_t println(void); virtual void flush() { /* Empty implementation for backward compatibility */ } 150: 08 95 ret 00000152 <_ZN5Print17availableForWriteEv>: return write((const uint8_t *)buffer, size); } // default to zero, meaning "a single write may block" // should be overriden by subclasses with buffering virtual int availableForWrite() { return 0; } 152: 80 e0 ldi r24, 0x00 ; 0 154: 90 e0 ldi r25, 0x00 ; 0 156: 08 95 ret 00000158 <_ZN14HardwareSerial17availableForWriteEv>: { #if (SERIAL_TX_BUFFER_SIZE>256) uint8_t oldSREG = SREG; cli(); #endif tx_buffer_index_t head = _tx_buffer_head; 158: fc 01 movw r30, r24 15a: 53 8d ldd r21, Z+27 ; 0x1b tx_buffer_index_t tail = _tx_buffer_tail; 15c: 44 8d ldd r20, Z+28 ; 0x1c 15e: 25 2f mov r18, r21 160: 30 e0 ldi r19, 0x00 ; 0 162: 84 2f mov r24, r20 164: 90 e0 ldi r25, 0x00 ; 0 #if (SERIAL_TX_BUFFER_SIZE>256) SREG = oldSREG; #endif if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail; 166: 82 1b sub r24, r18 168: 93 0b sbc r25, r19 16a: 54 17 cp r21, r20 16c: 10 f0 brcs .+4 ; 0x172 <_ZN14HardwareSerial17availableForWriteEv+0x1a> 16e: cf 96 adiw r24, 0x3f ; 63 170: 08 95 ret return tail - head - 1; 172: 01 97 sbiw r24, 0x01 ; 1 } 174: 08 95 ret 00000176 <_ZN14HardwareSerial4readEv>: return _rx_buffer[_rx_buffer_tail]; } } int HardwareSerial::read(void) { 176: fc 01 movw r30, r24 // if the head isn't ahead of the tail, we don't have any characters if (_rx_buffer_head == _rx_buffer_tail) { 178: 91 8d ldd r25, Z+25 ; 0x19 17a: 82 8d ldd r24, Z+26 ; 0x1a 17c: 98 17 cp r25, r24 17e: 61 f0 breq .+24 ; 0x198 <_ZN14HardwareSerial4readEv+0x22> return -1; } else { unsigned char c = _rx_buffer[_rx_buffer_tail]; 180: 82 8d ldd r24, Z+26 ; 0x1a 182: df 01 movw r26, r30 184: a8 0f add r26, r24 186: b1 1d adc r27, r1 188: 5d 96 adiw r26, 0x1d ; 29 18a: 8c 91 ld r24, X _rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE; 18c: 92 8d ldd r25, Z+26 ; 0x1a 18e: 9f 5f subi r25, 0xFF ; 255 190: 9f 73 andi r25, 0x3F ; 63 192: 92 8f std Z+26, r25 ; 0x1a return c; 194: 90 e0 ldi r25, 0x00 ; 0 196: 08 95 ret int HardwareSerial::read(void) { // if the head isn't ahead of the tail, we don't have any characters if (_rx_buffer_head == _rx_buffer_tail) { return -1; 198: 8f ef ldi r24, 0xFF ; 255 19a: 9f ef ldi r25, 0xFF ; 255 } else { unsigned char c = _rx_buffer[_rx_buffer_tail]; _rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE; return c; } } 19c: 08 95 ret 0000019e <_ZN14HardwareSerial4peekEv>: { return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE; } int HardwareSerial::peek(void) { 19e: fc 01 movw r30, r24 if (_rx_buffer_head == _rx_buffer_tail) { 1a0: 91 8d ldd r25, Z+25 ; 0x19 1a2: 82 8d ldd r24, Z+26 ; 0x1a 1a4: 98 17 cp r25, r24 1a6: 31 f0 breq .+12 ; 0x1b4 <_ZN14HardwareSerial4peekEv+0x16> return -1; } else { return _rx_buffer[_rx_buffer_tail]; 1a8: 82 8d ldd r24, Z+26 ; 0x1a 1aa: e8 0f add r30, r24 1ac: f1 1d adc r31, r1 1ae: 85 8d ldd r24, Z+29 ; 0x1d 1b0: 90 e0 ldi r25, 0x00 ; 0 1b2: 08 95 ret } int HardwareSerial::peek(void) { if (_rx_buffer_head == _rx_buffer_tail) { return -1; 1b4: 8f ef ldi r24, 0xFF ; 255 1b6: 9f ef ldi r25, 0xFF ; 255 } else { return _rx_buffer[_rx_buffer_tail]; } } 1b8: 08 95 ret 000001ba <_ZN14HardwareSerial9availableEv>: // clear any received data _rx_buffer_head = _rx_buffer_tail; } int HardwareSerial::available(void) { 1ba: fc 01 movw r30, r24 return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE; 1bc: 91 8d ldd r25, Z+25 ; 0x19 1be: 22 8d ldd r18, Z+26 ; 0x1a 1c0: 89 2f mov r24, r25 1c2: 90 e0 ldi r25, 0x00 ; 0 1c4: 80 5c subi r24, 0xC0 ; 192 1c6: 9f 4f sbci r25, 0xFF ; 255 1c8: 82 1b sub r24, r18 1ca: 91 09 sbc r25, r1 } 1cc: 8f 73 andi r24, 0x3F ; 63 1ce: 99 27 eor r25, r25 1d0: 08 95 ret 000001d2 <_Z17Serial0_availablev>: #endif // Function that can be weakly referenced by serialEventRun to prevent // pulling in this file if it's not otherwise used. bool Serial0_available() { return Serial.available(); 1d2: 80 e3 ldi r24, 0x30 ; 48 1d4: 91 e0 ldi r25, 0x01 ; 1 1d6: 0e 94 dd 00 call 0x1ba ; 0x1ba <_ZN14HardwareSerial9availableEv> 1da: 21 e0 ldi r18, 0x01 ; 1 1dc: 89 2b or r24, r25 1de: 09 f4 brne .+2 ; 0x1e2 <_Z17Serial0_availablev+0x10> 1e0: 20 e0 ldi r18, 0x00 ; 0 } 1e2: 82 2f mov r24, r18 1e4: 08 95 ret 000001e6 <_ZN14HardwareSerial17_tx_udr_empty_irqEv>: } // Actual interrupt handlers ////////////////////////////////////////////////////////////// void HardwareSerial::_tx_udr_empty_irq(void) { 1e6: fc 01 movw r30, r24 // If interrupts are enabled, there must be more data in the output // buffer. Send the next byte unsigned char c = _tx_buffer[_tx_buffer_tail]; 1e8: 84 8d ldd r24, Z+28 ; 0x1c 1ea: df 01 movw r26, r30 1ec: a8 0f add r26, r24 1ee: b1 1d adc r27, r1 1f0: a3 5a subi r26, 0xA3 ; 163 1f2: bf 4f sbci r27, 0xFF ; 255 1f4: 2c 91 ld r18, X _tx_buffer_tail = (_tx_buffer_tail + 1) % SERIAL_TX_BUFFER_SIZE; 1f6: 84 8d ldd r24, Z+28 ; 0x1c 1f8: 90 e0 ldi r25, 0x00 ; 0 1fa: 01 96 adiw r24, 0x01 ; 1 1fc: 8f 73 andi r24, 0x3F ; 63 1fe: 99 27 eor r25, r25 200: 84 8f std Z+28, r24 ; 0x1c *_udr = c; 202: a6 89 ldd r26, Z+22 ; 0x16 204: b7 89 ldd r27, Z+23 ; 0x17 206: 2c 93 st X, r18 // clear the TXC bit -- "can be cleared by writing a one to its bit // location". This makes sure flush() won't return until the bytes // actually got written sbi(*_ucsra, TXC0); 208: a0 89 ldd r26, Z+16 ; 0x10 20a: b1 89 ldd r27, Z+17 ; 0x11 20c: 8c 91 ld r24, X 20e: 80 64 ori r24, 0x40 ; 64 210: 8c 93 st X, r24 if (_tx_buffer_head == _tx_buffer_tail) { 212: 93 8d ldd r25, Z+27 ; 0x1b 214: 84 8d ldd r24, Z+28 ; 0x1c 216: 98 13 cpse r25, r24 218: 06 c0 rjmp .+12 ; 0x226 <_ZN14HardwareSerial17_tx_udr_empty_irqEv+0x40> // Buffer empty, so disable interrupts cbi(*_ucsrb, UDRIE0); 21a: 02 88 ldd r0, Z+18 ; 0x12 21c: f3 89 ldd r31, Z+19 ; 0x13 21e: e0 2d mov r30, r0 220: 80 81 ld r24, Z 222: 8f 7d andi r24, 0xDF ; 223 224: 80 83 st Z, r24 226: 08 95 ret 00000228 <_ZN14HardwareSerial5writeEh>: // If we get here, nothing is queued anymore (DRIE is disabled) and // the hardware finished tranmission (TXC is set). } size_t HardwareSerial::write(uint8_t c) { 228: ef 92 push r14 22a: ff 92 push r15 22c: 0f 93 push r16 22e: 1f 93 push r17 230: cf 93 push r28 232: df 93 push r29 234: ec 01 movw r28, r24 _written = true; 236: 81 e0 ldi r24, 0x01 ; 1 238: 88 8f std Y+24, r24 ; 0x18 // If the buffer and the data register is empty, just write the byte // to the data register and be done. This shortcut helps // significantly improve the effective datarate at high (> // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { 23a: 9b 8d ldd r25, Y+27 ; 0x1b 23c: 8c 8d ldd r24, Y+28 ; 0x1c 23e: 98 13 cpse r25, r24 240: 05 c0 rjmp .+10 ; 0x24c <_ZN14HardwareSerial5writeEh+0x24> 242: e8 89 ldd r30, Y+16 ; 0x10 244: f9 89 ldd r31, Y+17 ; 0x11 246: 80 81 ld r24, Z 248: 85 fd sbrc r24, 5 24a: 24 c0 rjmp .+72 ; 0x294 <_ZN14HardwareSerial5writeEh+0x6c> 24c: f6 2e mov r15, r22 *_udr = c; sbi(*_ucsra, TXC0); return 1; } tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE; 24e: 0b 8d ldd r16, Y+27 ; 0x1b 250: 10 e0 ldi r17, 0x00 ; 0 252: 0f 5f subi r16, 0xFF ; 255 254: 1f 4f sbci r17, 0xFF ; 255 256: 0f 73 andi r16, 0x3F ; 63 258: 11 27 eor r17, r17 25a: e0 2e mov r14, r16 // If the output buffer is full, there's nothing for it other than to // wait for the interrupt handler to empty it a bit while (i == _tx_buffer_tail) { 25c: 8c 8d ldd r24, Y+28 ; 0x1c 25e: e8 12 cpse r14, r24 260: 0c c0 rjmp .+24 ; 0x27a <_ZN14HardwareSerial5writeEh+0x52> if (bit_is_clear(SREG, SREG_I)) { 262: 0f b6 in r0, 0x3f ; 63 264: 07 fc sbrc r0, 7 266: fa cf rjmp .-12 ; 0x25c <_ZN14HardwareSerial5writeEh+0x34> // Interrupts are disabled, so we'll have to poll the data // register empty flag ourselves. If it is set, pretend an // interrupt has happened and call the handler to free up // space for us. if(bit_is_set(*_ucsra, UDRE0)) 268: e8 89 ldd r30, Y+16 ; 0x10 26a: f9 89 ldd r31, Y+17 ; 0x11 26c: 80 81 ld r24, Z 26e: 85 ff sbrs r24, 5 270: f5 cf rjmp .-22 ; 0x25c <_ZN14HardwareSerial5writeEh+0x34> _tx_udr_empty_irq(); 272: ce 01 movw r24, r28 274: 0e 94 f3 00 call 0x1e6 ; 0x1e6 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> 278: f1 cf rjmp .-30 ; 0x25c <_ZN14HardwareSerial5writeEh+0x34> } else { // nop, the interrupt handler will free up space for us } } _tx_buffer[_tx_buffer_head] = c; 27a: 8b 8d ldd r24, Y+27 ; 0x1b 27c: fe 01 movw r30, r28 27e: e8 0f add r30, r24 280: f1 1d adc r31, r1 282: e3 5a subi r30, 0xA3 ; 163 284: ff 4f sbci r31, 0xFF ; 255 286: f0 82 st Z, r15 _tx_buffer_head = i; 288: 0b 8f std Y+27, r16 ; 0x1b sbi(*_ucsrb, UDRIE0); 28a: ea 89 ldd r30, Y+18 ; 0x12 28c: fb 89 ldd r31, Y+19 ; 0x13 28e: 80 81 ld r24, Z 290: 80 62 ori r24, 0x20 ; 32 292: 07 c0 rjmp .+14 ; 0x2a2 <_ZN14HardwareSerial5writeEh+0x7a> // If the buffer and the data register is empty, just write the byte // to the data register and be done. This shortcut helps // significantly improve the effective datarate at high (> // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { *_udr = c; 294: ee 89 ldd r30, Y+22 ; 0x16 296: ff 89 ldd r31, Y+23 ; 0x17 298: 60 83 st Z, r22 sbi(*_ucsra, TXC0); 29a: e8 89 ldd r30, Y+16 ; 0x10 29c: f9 89 ldd r31, Y+17 ; 0x11 29e: 80 81 ld r24, Z 2a0: 80 64 ori r24, 0x40 ; 64 2a2: 80 83 st Z, r24 _tx_buffer_head = i; sbi(*_ucsrb, UDRIE0); return 1; } 2a4: 81 e0 ldi r24, 0x01 ; 1 2a6: 90 e0 ldi r25, 0x00 ; 0 2a8: df 91 pop r29 2aa: cf 91 pop r28 2ac: 1f 91 pop r17 2ae: 0f 91 pop r16 2b0: ff 90 pop r15 2b2: ef 90 pop r14 2b4: 08 95 ret 000002b6 <_ZN14HardwareSerial5flushEv>: if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail; return tail - head - 1; } void HardwareSerial::flush() { 2b6: cf 93 push r28 2b8: df 93 push r29 2ba: ec 01 movw r28, r24 // If we have never written a byte, no need to flush. This special // case is needed since there is no way to force the TXC (transmit // complete) bit to 1 during initialization if (!_written) 2bc: 88 8d ldd r24, Y+24 ; 0x18 2be: 88 23 and r24, r24 2c0: c9 f0 breq .+50 ; 0x2f4 <_ZN14HardwareSerial5flushEv+0x3e> return; while (bit_is_set(*_ucsrb, UDRIE0) || bit_is_clear(*_ucsra, TXC0)) { 2c2: ea 89 ldd r30, Y+18 ; 0x12 2c4: fb 89 ldd r31, Y+19 ; 0x13 2c6: 80 81 ld r24, Z 2c8: 85 fd sbrc r24, 5 2ca: 05 c0 rjmp .+10 ; 0x2d6 <_ZN14HardwareSerial5flushEv+0x20> 2cc: a8 89 ldd r26, Y+16 ; 0x10 2ce: b9 89 ldd r27, Y+17 ; 0x11 2d0: 8c 91 ld r24, X 2d2: 86 fd sbrc r24, 6 2d4: 0f c0 rjmp .+30 ; 0x2f4 <_ZN14HardwareSerial5flushEv+0x3e> if (bit_is_clear(SREG, SREG_I) && bit_is_set(*_ucsrb, UDRIE0)) 2d6: 0f b6 in r0, 0x3f ; 63 2d8: 07 fc sbrc r0, 7 2da: f5 cf rjmp .-22 ; 0x2c6 <_ZN14HardwareSerial5flushEv+0x10> 2dc: 80 81 ld r24, Z 2de: 85 ff sbrs r24, 5 2e0: f2 cf rjmp .-28 ; 0x2c6 <_ZN14HardwareSerial5flushEv+0x10> // Interrupts are globally disabled, but the DR empty // interrupt should be enabled, so poll the DR empty flag to // prevent deadlock if (bit_is_set(*_ucsra, UDRE0)) 2e2: a8 89 ldd r26, Y+16 ; 0x10 2e4: b9 89 ldd r27, Y+17 ; 0x11 2e6: 8c 91 ld r24, X 2e8: 85 ff sbrs r24, 5 2ea: ed cf rjmp .-38 ; 0x2c6 <_ZN14HardwareSerial5flushEv+0x10> _tx_udr_empty_irq(); 2ec: ce 01 movw r24, r28 2ee: 0e 94 f3 00 call 0x1e6 ; 0x1e6 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> 2f2: e7 cf rjmp .-50 ; 0x2c2 <_ZN14HardwareSerial5flushEv+0xc> } // If we get here, nothing is queued anymore (DRIE is disabled) and // the hardware finished tranmission (TXC is set). } 2f4: df 91 pop r29 2f6: cf 91 pop r28 2f8: 08 95 ret 000002fa <_Z14serialEventRunv>: #endif void serialEventRun(void) { #if defined(HAVE_HWSERIAL0) if (Serial0_available && serialEvent && Serial0_available()) serialEvent(); 2fa: 80 e0 ldi r24, 0x00 ; 0 2fc: 90 e0 ldi r25, 0x00 ; 0 2fe: 89 2b or r24, r25 300: 29 f0 breq .+10 ; 0x30c <_Z14serialEventRunv+0x12> 302: 0e 94 e9 00 call 0x1d2 ; 0x1d2 <_Z17Serial0_availablev> 306: 81 11 cpse r24, r1 308: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 30c: 08 95 ret 0000030e : return m; } unsigned long micros() { unsigned long m; uint8_t oldSREG = SREG, t; 30e: 3f b7 in r19, 0x3f ; 63 cli(); 310: f8 94 cli m = timer0_overflow_count; 312: 80 91 27 01 lds r24, 0x0127 316: 90 91 28 01 lds r25, 0x0128 31a: a0 91 29 01 lds r26, 0x0129 31e: b0 91 2a 01 lds r27, 0x012A #if defined(TCNT0) t = TCNT0; 322: 26 b5 in r18, 0x26 ; 38 #else #error TIMER 0 not defined #endif #ifdef TIFR0 if ((TIFR0 & _BV(TOV0)) && (t < 255)) 324: a8 9b sbis 0x15, 0 ; 21 326: 05 c0 rjmp .+10 ; 0x332 328: 2f 3f cpi r18, 0xFF ; 255 32a: 19 f0 breq .+6 ; 0x332 m++; 32c: 01 96 adiw r24, 0x01 ; 1 32e: a1 1d adc r26, r1 330: b1 1d adc r27, r1 #else if ((TIFR & _BV(TOV0)) && (t < 255)) m++; #endif SREG = oldSREG; 332: 3f bf out 0x3f, r19 ; 63 return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond()); 334: ba 2f mov r27, r26 336: a9 2f mov r26, r25 338: 98 2f mov r25, r24 33a: 88 27 eor r24, r24 33c: 82 0f add r24, r18 33e: 91 1d adc r25, r1 340: a1 1d adc r26, r1 342: b1 1d adc r27, r1 344: bc 01 movw r22, r24 346: cd 01 movw r24, r26 348: 42 e0 ldi r20, 0x02 ; 2 34a: 66 0f add r22, r22 34c: 77 1f adc r23, r23 34e: 88 1f adc r24, r24 350: 99 1f adc r25, r25 352: 4a 95 dec r20 354: d1 f7 brne .-12 ; 0x34a } 356: 08 95 ret 00000358 <_ZN5Print5writeEPKc.constprop.13>: int getWriteError() { return write_error; } void clearWriteError() { setWriteError(0); } virtual size_t write(uint8_t) = 0; size_t write(const char *str) { if (str == NULL) return 0; 358: 00 97 sbiw r24, 0x00 ; 0 35a: 69 f0 breq .+26 ; 0x376 <_ZN5Print5writeEPKc.constprop.13+0x1e> return write((const uint8_t *)str, strlen(str)); 35c: fc 01 movw r30, r24 35e: 01 90 ld r0, Z+ 360: 00 20 and r0, r0 362: e9 f7 brne .-6 ; 0x35e <_ZN5Print5writeEPKc.constprop.13+0x6> 364: 31 97 sbiw r30, 0x01 ; 1 366: af 01 movw r20, r30 368: 48 1b sub r20, r24 36a: 59 0b sbc r21, r25 36c: bc 01 movw r22, r24 36e: 80 e3 ldi r24, 0x30 ; 48 370: 91 e0 ldi r25, 0x01 ; 1 372: 0c 94 7d 00 jmp 0xfa ; 0xfa <_ZN5Print5writeEPKhj> } 376: 80 e0 ldi r24, 0x00 ; 0 378: 90 e0 ldi r25, 0x00 ; 0 37a: 08 95 ret 0000037c <__cxa_pure_virtual>: extern "C" void __cxa_deleted_virtual(void) __attribute__ ((__noreturn__)); void __cxa_pure_virtual(void) { // We might want to write some diagnostics to uart in this case //std::terminate(); abort(); 37c: 0e 94 44 04 call 0x888 ; 0x888 00000380 <__vector_19>: #elif defined(USART_UDRE_vect) ISR(USART_UDRE_vect) #else #error "Don't know what the Data Register Empty vector is called for Serial" #endif { 380: 1f 92 push r1 382: 0f 92 push r0 384: 0f b6 in r0, 0x3f ; 63 386: 0f 92 push r0 388: 11 24 eor r1, r1 38a: 2f 93 push r18 38c: 3f 93 push r19 38e: 4f 93 push r20 390: 5f 93 push r21 392: 6f 93 push r22 394: 7f 93 push r23 396: 8f 93 push r24 398: 9f 93 push r25 39a: af 93 push r26 39c: bf 93 push r27 39e: ef 93 push r30 3a0: ff 93 push r31 Serial._tx_udr_empty_irq(); 3a2: 80 e3 ldi r24, 0x30 ; 48 3a4: 91 e0 ldi r25, 0x01 ; 1 3a6: 0e 94 f3 00 call 0x1e6 ; 0x1e6 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> } 3aa: ff 91 pop r31 3ac: ef 91 pop r30 3ae: bf 91 pop r27 3b0: af 91 pop r26 3b2: 9f 91 pop r25 3b4: 8f 91 pop r24 3b6: 7f 91 pop r23 3b8: 6f 91 pop r22 3ba: 5f 91 pop r21 3bc: 4f 91 pop r20 3be: 3f 91 pop r19 3c0: 2f 91 pop r18 3c2: 0f 90 pop r0 3c4: 0f be out 0x3f, r0 ; 63 3c6: 0f 90 pop r0 3c8: 1f 90 pop r1 3ca: 18 95 reti 000003cc <__vector_18>: #elif defined(USART_RXC_vect) ISR(USART_RXC_vect) // ATmega8 #else #error "Don't know what the Data Received vector is called for Serial" #endif { 3cc: 1f 92 push r1 3ce: 0f 92 push r0 3d0: 0f b6 in r0, 0x3f ; 63 3d2: 0f 92 push r0 3d4: 11 24 eor r1, r1 3d6: 2f 93 push r18 3d8: 8f 93 push r24 3da: 9f 93 push r25 3dc: ef 93 push r30 3de: ff 93 push r31 // Actual interrupt handlers ////////////////////////////////////////////////////////////// void HardwareSerial::_rx_complete_irq(void) { if (bit_is_clear(*_ucsra, UPE0)) { 3e0: e0 91 40 01 lds r30, 0x0140 3e4: f0 91 41 01 lds r31, 0x0141 3e8: 80 81 ld r24, Z 3ea: e0 91 46 01 lds r30, 0x0146 3ee: f0 91 47 01 lds r31, 0x0147 3f2: 82 fd sbrc r24, 2 3f4: 12 c0 rjmp .+36 ; 0x41a <__LOCK_REGION_LENGTH__+0x1a> // No Parity error, read byte and store it in the buffer if there is // room unsigned char c = *_udr; 3f6: 90 81 ld r25, Z rx_buffer_index_t i = (unsigned int)(_rx_buffer_head + 1) % SERIAL_RX_BUFFER_SIZE; 3f8: 80 91 49 01 lds r24, 0x0149 3fc: 8f 5f subi r24, 0xFF ; 255 3fe: 8f 73 andi r24, 0x3F ; 63 // if we should be storing the received character into the location // just before the tail (meaning that the head would advance to the // current location of the tail), we're about to overflow the buffer // and so we don't write the character or advance the head. if (i != _rx_buffer_tail) { 400: 20 91 4a 01 lds r18, 0x014A 404: 82 17 cp r24, r18 406: 51 f0 breq .+20 ; 0x41c <__LOCK_REGION_LENGTH__+0x1c> _rx_buffer[_rx_buffer_head] = c; 408: e0 91 49 01 lds r30, 0x0149 40c: f0 e0 ldi r31, 0x00 ; 0 40e: e0 5d subi r30, 0xD0 ; 208 410: fe 4f sbci r31, 0xFE ; 254 412: 95 8f std Z+29, r25 ; 0x1d _rx_buffer_head = i; 414: 80 93 49 01 sts 0x0149, r24 418: 01 c0 rjmp .+2 ; 0x41c <__LOCK_REGION_LENGTH__+0x1c> } } else { // Parity error, read byte but discard it *_udr; 41a: 80 81 ld r24, Z Serial._rx_complete_irq(); } 41c: ff 91 pop r31 41e: ef 91 pop r30 420: 9f 91 pop r25 422: 8f 91 pop r24 424: 2f 91 pop r18 426: 0f 90 pop r0 428: 0f be out 0x3f, r0 ; 63 42a: 0f 90 pop r0 42c: 1f 90 pop r1 42e: 18 95 reti 00000430 <__vector_16>: #if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ISR(TIM0_OVF_vect) #else ISR(TIMER0_OVF_vect) #endif { 430: 1f 92 push r1 432: 0f 92 push r0 434: 0f b6 in r0, 0x3f ; 63 436: 0f 92 push r0 438: 11 24 eor r1, r1 43a: 2f 93 push r18 43c: 3f 93 push r19 43e: 8f 93 push r24 440: 9f 93 push r25 442: af 93 push r26 444: bf 93 push r27 // copy these to local variables so they can be stored in registers // (volatile variables must be read from memory on every access) unsigned long m = timer0_millis; 446: 80 91 23 01 lds r24, 0x0123 44a: 90 91 24 01 lds r25, 0x0124 44e: a0 91 25 01 lds r26, 0x0125 452: b0 91 26 01 lds r27, 0x0126 unsigned char f = timer0_fract; 456: 30 91 22 01 lds r19, 0x0122 m += MILLIS_INC; f += FRACT_INC; 45a: 23 e0 ldi r18, 0x03 ; 3 45c: 23 0f add r18, r19 if (f >= FRACT_MAX) { 45e: 2d 37 cpi r18, 0x7D ; 125 460: 20 f4 brcc .+8 ; 0x46a <__vector_16+0x3a> // copy these to local variables so they can be stored in registers // (volatile variables must be read from memory on every access) unsigned long m = timer0_millis; unsigned char f = timer0_fract; m += MILLIS_INC; 462: 01 96 adiw r24, 0x01 ; 1 464: a1 1d adc r26, r1 466: b1 1d adc r27, r1 468: 05 c0 rjmp .+10 ; 0x474 <__vector_16+0x44> f += FRACT_INC; if (f >= FRACT_MAX) { f -= FRACT_MAX; 46a: 26 e8 ldi r18, 0x86 ; 134 46c: 23 0f add r18, r19 m += 1; 46e: 02 96 adiw r24, 0x02 ; 2 470: a1 1d adc r26, r1 472: b1 1d adc r27, r1 } timer0_fract = f; 474: 20 93 22 01 sts 0x0122, r18 timer0_millis = m; 478: 80 93 23 01 sts 0x0123, r24 47c: 90 93 24 01 sts 0x0124, r25 480: a0 93 25 01 sts 0x0125, r26 484: b0 93 26 01 sts 0x0126, r27 timer0_overflow_count++; 488: 80 91 27 01 lds r24, 0x0127 48c: 90 91 28 01 lds r25, 0x0128 490: a0 91 29 01 lds r26, 0x0129 494: b0 91 2a 01 lds r27, 0x012A 498: 01 96 adiw r24, 0x01 ; 1 49a: a1 1d adc r26, r1 49c: b1 1d adc r27, r1 49e: 80 93 27 01 sts 0x0127, r24 4a2: 90 93 28 01 sts 0x0128, r25 4a6: a0 93 29 01 sts 0x0129, r26 4aa: b0 93 2a 01 sts 0x012A, r27 } 4ae: bf 91 pop r27 4b0: af 91 pop r26 4b2: 9f 91 pop r25 4b4: 8f 91 pop r24 4b6: 3f 91 pop r19 4b8: 2f 91 pop r18 4ba: 0f 90 pop r0 4bc: 0f be out 0x3f, r0 ; 63 4be: 0f 90 pop r0 4c0: 1f 90 pop r1 4c2: 18 95 reti 000004c4 <__vector_1>: } //end if }//end loop ISR(INT0_vect) { // INT0 interrupt service routine 4c4: 1f 92 push r1 4c6: 0f 92 push r0 4c8: 0f b6 in r0, 0x3f ; 63 4ca: 0f 92 push r0 4cc: 11 24 eor r1, r1 4ce: 2f 93 push r18 4d0: 3f 93 push r19 4d2: 4f 93 push r20 4d4: 5f 93 push r21 4d6: 6f 93 push r22 4d8: 7f 93 push r23 4da: 8f 93 push r24 4dc: 9f 93 push r25 4de: af 93 push r26 4e0: bf 93 push r27 4e2: ef 93 push r30 4e4: ff 93 push r31 unsigned long currenttime=micros(); 4e6: 0e 94 87 01 call 0x30e ; 0x30e if ((PIND & (1 << PIND2))) { 4ea: 4a 9b sbis 0x09, 2 ; 9 4ec: 0c c0 rjmp .+24 ; 0x506 <__vector_1+0x42> starttime=currenttime; 4ee: 60 93 1e 01 sts 0x011E, r22 4f2: 70 93 1f 01 sts 0x011F, r23 4f6: 80 93 20 01 sts 0x0120, r24 4fa: 90 93 21 01 sts 0x0121, r25 EICRA = 0b00000010; // INT0, falling edge 4fe: 82 e0 ldi r24, 0x02 ; 2 500: 80 93 69 00 sts 0x0069, r24 504: 2a c0 rjmp .+84 ; 0x55a <__vector_1+0x96> } else { endtime=currenttime; 506: 60 93 1a 01 sts 0x011A, r22 50a: 70 93 1b 01 sts 0x011B, r23 50e: 80 93 1c 01 sts 0x011C, r24 512: 90 93 1d 01 sts 0x011D, r25 EICRA = 0b00000011; // INT0, rising edge 516: 83 e0 ldi r24, 0x03 ; 3 518: 80 93 69 00 sts 0x0069, r24 duration=endtime-starttime; 51c: 80 91 1a 01 lds r24, 0x011A 520: 90 91 1b 01 lds r25, 0x011B 524: a0 91 1c 01 lds r26, 0x011C 528: b0 91 1d 01 lds r27, 0x011D 52c: 40 91 1e 01 lds r20, 0x011E 530: 50 91 1f 01 lds r21, 0x011F 534: 60 91 20 01 lds r22, 0x0120 538: 70 91 21 01 lds r23, 0x0121 53c: 84 1b sub r24, r20 53e: 95 0b sbc r25, r21 540: a6 0b sbc r26, r22 542: b7 0b sbc r27, r23 544: 80 93 2b 01 sts 0x012B, r24 548: 90 93 2c 01 sts 0x012C, r25 54c: a0 93 2d 01 sts 0x012D, r26 550: b0 93 2e 01 sts 0x012E, r27 newVal=true; 554: 81 e0 ldi r24, 0x01 ; 1 556: 80 93 2f 01 sts 0x012F, r24 } EIFR |= 0b00000001; //clear INT0 flag 55a: e0 9a sbi 0x1c, 0 ; 28 }// end ISR 55c: ff 91 pop r31 55e: ef 91 pop r30 560: bf 91 pop r27 562: af 91 pop r26 564: 9f 91 pop r25 566: 8f 91 pop r24 568: 7f 91 pop r23 56a: 6f 91 pop r22 56c: 5f 91 pop r21 56e: 4f 91 pop r20 570: 3f 91 pop r19 572: 2f 91 pop r18 574: 0f 90 pop r0 576: 0f be out 0x3f, r0 ; 63 578: 0f 90 pop r0 57a: 1f 90 pop r1 57c: 18 95 reti 0000057e
: void setupUSB() __attribute__((weak)); void setupUSB() { } int main(void) { 57e: cf 93 push r28 580: df 93 push r29 582: cd b7 in r28, 0x3d ; 61 584: de b7 in r29, 0x3e ; 62 586: a1 97 sbiw r28, 0x21 ; 33 588: 0f b6 in r0, 0x3f ; 63 58a: f8 94 cli 58c: de bf out 0x3e, r29 ; 62 58e: 0f be out 0x3f, r0 ; 63 590: cd bf out 0x3d, r28 ; 61 void init() { // this needs to be called before setup() or some functions won't // work there sei(); 592: 78 94 sei // on the ATmega168, timer 0 is also used for fast hardware pwm // (using phase-correct PWM would mean that timer 0 overflowed half as often // resulting in different millis() behavior on the ATmega8 and ATmega168) #if defined(TCCR0A) && defined(WGM01) sbi(TCCR0A, WGM01); 594: 84 b5 in r24, 0x24 ; 36 596: 82 60 ori r24, 0x02 ; 2 598: 84 bd out 0x24, r24 ; 36 sbi(TCCR0A, WGM00); 59a: 84 b5 in r24, 0x24 ; 36 59c: 81 60 ori r24, 0x01 ; 1 59e: 84 bd out 0x24, r24 ; 36 // this combination is for the standard atmega8 sbi(TCCR0, CS01); sbi(TCCR0, CS00); #elif defined(TCCR0B) && defined(CS01) && defined(CS00) // this combination is for the standard 168/328/1280/2560 sbi(TCCR0B, CS01); 5a0: 85 b5 in r24, 0x25 ; 37 5a2: 82 60 ori r24, 0x02 ; 2 5a4: 85 bd out 0x25, r24 ; 37 sbi(TCCR0B, CS00); 5a6: 85 b5 in r24, 0x25 ; 37 5a8: 81 60 ori r24, 0x01 ; 1 5aa: 85 bd out 0x25, r24 ; 37 // enable timer 0 overflow interrupt #if defined(TIMSK) && defined(TOIE0) sbi(TIMSK, TOIE0); #elif defined(TIMSK0) && defined(TOIE0) sbi(TIMSK0, TOIE0); 5ac: 80 91 6e 00 lds r24, 0x006E 5b0: 81 60 ori r24, 0x01 ; 1 5b2: 80 93 6e 00 sts 0x006E, r24 // this is better for motors as it ensures an even waveform // note, however, that fast pwm mode can achieve a frequency of up // 8 MHz (with a 16 MHz clock) at 50% duty cycle #if defined(TCCR1B) && defined(CS11) && defined(CS10) TCCR1B = 0; 5b6: 10 92 81 00 sts 0x0081, r1 // set timer 1 prescale factor to 64 sbi(TCCR1B, CS11); 5ba: 80 91 81 00 lds r24, 0x0081 5be: 82 60 ori r24, 0x02 ; 2 5c0: 80 93 81 00 sts 0x0081, r24 #if F_CPU >= 8000000L sbi(TCCR1B, CS10); 5c4: 80 91 81 00 lds r24, 0x0081 5c8: 81 60 ori r24, 0x01 ; 1 5ca: 80 93 81 00 sts 0x0081, r24 sbi(TCCR1, CS10); #endif #endif // put timer 1 in 8-bit phase correct pwm mode #if defined(TCCR1A) && defined(WGM10) sbi(TCCR1A, WGM10); 5ce: 80 91 80 00 lds r24, 0x0080 5d2: 81 60 ori r24, 0x01 ; 1 5d4: 80 93 80 00 sts 0x0080, r24 // set timer 2 prescale factor to 64 #if defined(TCCR2) && defined(CS22) sbi(TCCR2, CS22); #elif defined(TCCR2B) && defined(CS22) sbi(TCCR2B, CS22); 5d8: 80 91 b1 00 lds r24, 0x00B1 5dc: 84 60 ori r24, 0x04 ; 4 5de: 80 93 b1 00 sts 0x00B1, r24 // configure timer 2 for phase correct pwm (8-bit) #if defined(TCCR2) && defined(WGM20) sbi(TCCR2, WGM20); #elif defined(TCCR2A) && defined(WGM20) sbi(TCCR2A, WGM20); 5e2: 80 91 b0 00 lds r24, 0x00B0 5e6: 81 60 ori r24, 0x01 ; 1 5e8: 80 93 b0 00 sts 0x00B0, r24 #endif #if defined(ADCSRA) // set a2d prescaler so we are inside the desired 50-200 KHz range. #if F_CPU >= 16000000 // 16 MHz / 128 = 125 KHz sbi(ADCSRA, ADPS2); 5ec: 80 91 7a 00 lds r24, 0x007A 5f0: 84 60 ori r24, 0x04 ; 4 5f2: 80 93 7a 00 sts 0x007A, r24 sbi(ADCSRA, ADPS1); 5f6: 80 91 7a 00 lds r24, 0x007A 5fa: 82 60 ori r24, 0x02 ; 2 5fc: 80 93 7a 00 sts 0x007A, r24 sbi(ADCSRA, ADPS0); 600: 80 91 7a 00 lds r24, 0x007A 604: 81 60 ori r24, 0x01 ; 1 606: 80 93 7a 00 sts 0x007A, r24 cbi(ADCSRA, ADPS2); cbi(ADCSRA, ADPS1); sbi(ADCSRA, ADPS0); #endif // enable a2d conversions sbi(ADCSRA, ADEN); 60a: 80 91 7a 00 lds r24, 0x007A 60e: 80 68 ori r24, 0x80 ; 128 610: 80 93 7a 00 sts 0x007A, r24 // here so they can be used as normal digital i/o; they will be // reconnected in Serial.begin() #if defined(UCSRB) UCSRB = 0; #elif defined(UCSR0B) UCSR0B = 0; 614: 10 92 c1 00 sts 0x00C1, r1 #include "wiring_private.h" #include "pins_arduino.h" void pinMode(uint8_t pin, uint8_t mode) { uint8_t bit = digitalPinToBitMask(pin); 618: e2 e9 ldi r30, 0x92 ; 146 61a: f0 e0 ldi r31, 0x00 ; 0 61c: 24 91 lpm r18, Z uint8_t port = digitalPinToPort(pin); 61e: ee e7 ldi r30, 0x7E ; 126 620: f0 e0 ldi r31, 0x00 ; 0 622: 84 91 lpm r24, Z volatile uint8_t *reg, *out; if (port == NOT_A_PIN) return; 624: 88 23 and r24, r24 626: c9 f0 breq .+50 ; 0x65a // JWS: can I let the optimizer do this? reg = portModeRegister(port); 628: 90 e0 ldi r25, 0x00 ; 0 62a: 88 0f add r24, r24 62c: 99 1f adc r25, r25 62e: fc 01 movw r30, r24 630: ee 58 subi r30, 0x8E ; 142 632: ff 4f sbci r31, 0xFF ; 255 634: 45 91 lpm r20, Z+ 636: 54 91 lpm r21, Z out = portOutputRegister(port); 638: fc 01 movw r30, r24 63a: e8 59 subi r30, 0x98 ; 152 63c: ff 4f sbci r31, 0xFF ; 255 63e: a5 91 lpm r26, Z+ 640: b4 91 lpm r27, Z if (mode == INPUT) { uint8_t oldSREG = SREG; 642: 9f b7 in r25, 0x3f ; 63 cli(); 644: f8 94 cli *reg &= ~bit; 646: fa 01 movw r30, r20 648: 80 81 ld r24, Z 64a: 20 95 com r18 64c: 82 23 and r24, r18 64e: 80 83 st Z, r24 *out &= ~bit; 650: 8c 91 ld r24, X 652: e2 2f mov r30, r18 654: e8 23 and r30, r24 656: ec 93 st X, r30 SREG = oldSREG; 658: 9f bf out 0x3f, r25 ; 63 void HardwareSerial::begin(unsigned long baud, byte config) { // Try u2x mode first uint16_t baud_setting = (F_CPU / 4 / baud - 1) / 2; *_ucsra = 1 << U2X0; 65a: e0 91 40 01 lds r30, 0x0140 65e: f0 91 41 01 lds r31, 0x0141 662: 82 e0 ldi r24, 0x02 ; 2 664: 80 83 st Z, r24 *_ucsra = 0; baud_setting = (F_CPU / 8 / baud - 1) / 2; } // assign the baud_setting, a.k.a. ubrr (USART Baud Rate Register) *_ubrrh = baud_setting >> 8; 666: e0 91 3c 01 lds r30, 0x013C 66a: f0 91 3d 01 lds r31, 0x013D 66e: 10 82 st Z, r1 *_ubrrl = baud_setting; 670: e0 91 3e 01 lds r30, 0x013E 674: f0 91 3f 01 lds r31, 0x013F 678: 8f ec ldi r24, 0xCF ; 207 67a: 80 83 st Z, r24 _written = false; 67c: 10 92 48 01 sts 0x0148, r1 //set the data bits, parity, and stop bits #if defined(__AVR_ATmega8__) config |= 0x80; // select UCSRC register (shared with UBRRH) #endif *_ucsrc = config; 680: e0 91 44 01 lds r30, 0x0144 684: f0 91 45 01 lds r31, 0x0145 688: 86 e0 ldi r24, 0x06 ; 6 68a: 80 83 st Z, r24 sbi(*_ucsrb, RXEN0); 68c: e0 91 42 01 lds r30, 0x0142 690: f0 91 43 01 lds r31, 0x0143 694: 80 81 ld r24, Z 696: 80 61 ori r24, 0x10 ; 16 698: 80 83 st Z, r24 sbi(*_ucsrb, TXEN0); 69a: e0 91 42 01 lds r30, 0x0142 69e: f0 91 43 01 lds r31, 0x0143 6a2: 80 81 ld r24, Z 6a4: 88 60 ori r24, 0x08 ; 8 6a6: 80 83 st Z, r24 sbi(*_ucsrb, RXCIE0); 6a8: e0 91 42 01 lds r30, 0x0142 6ac: f0 91 43 01 lds r31, 0x0143 6b0: 80 81 ld r24, Z 6b2: 80 68 ori r24, 0x80 ; 128 6b4: 80 83 st Z, r24 cbi(*_ucsrb, UDRIE0); 6b6: e0 91 42 01 lds r30, 0x0142 6ba: f0 91 43 01 lds r31, 0x0143 6be: 80 81 ld r24, Z 6c0: 8f 7d andi r24, 0xDF ; 223 6c2: 80 83 st Z, r24 void setup() { pinMode(pingPin, INPUT); // initialize serial communication: Serial.begin(9600); cli(); //we are disabling all interrupts 6c4: f8 94 cli EICRA = 0b00000011; // INT0, rising edge 6c6: 83 e0 ldi r24, 0x03 ; 3 6c8: 80 93 69 00 sts 0x0069, r24 EIFR = 0b00000001; //clear INT0 flag 6cc: 81 e0 ldi r24, 0x01 ; 1 6ce: 8c bb out 0x1c, r24 ; 28 EIMSK = 0b00000001; //enable INT0 6d0: 8d bb out 0x1d, r24 ; 29 sei(); // we re-enable interrupts including timer interrupts 6d2: 78 94 sei // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; 6d4: 9a e0 ldi r25, 0x0A ; 10 6d6: 89 2e mov r8, r25 6d8: 91 2c mov r9, r1 6da: a1 2c mov r10, r1 6dc: b1 2c mov r11, r1 } void loop() { if (newVal) { 6de: 80 91 2f 01 lds r24, 0x012F 6e2: 88 23 and r24, r24 6e4: 09 f4 brne .+2 ; 0x6e8 6e6: 78 c0 rjmp .+240 ; 0x7d8 Serial.print(duration); 6e8: c0 90 2b 01 lds r12, 0x012B 6ec: d0 90 2c 01 lds r13, 0x012C 6f0: e0 90 2d 01 lds r14, 0x012D 6f4: f0 90 2e 01 lds r15, 0x012E size_t Print::print(long n, int base) { if (base == 0) { return write(n); } else if (base == 10) { if (n < 0) { 6f8: f7 fe sbrs r15, 7 6fa: 26 c0 rjmp .+76 ; 0x748 return write(str); } size_t Print::print(char c) { return write(c); 6fc: e0 91 30 01 lds r30, 0x0130 700: f0 91 31 01 lds r31, 0x0131 704: 01 90 ld r0, Z+ 706: f0 81 ld r31, Z 708: e0 2d mov r30, r0 70a: 6d e2 ldi r22, 0x2D ; 45 70c: 80 e3 ldi r24, 0x30 ; 48 70e: 91 e0 ldi r25, 0x01 ; 1 710: 09 95 icall if (base == 0) { return write(n); } else if (base == 10) { if (n < 0) { int t = print('-'); n = -n; 712: 22 27 eor r18, r18 714: 33 27 eor r19, r19 716: a9 01 movw r20, r18 718: 2c 19 sub r18, r12 71a: 3d 09 sbc r19, r13 71c: 4e 09 sbc r20, r14 71e: 5f 09 sbc r21, r15 size_t Print::printNumber(unsigned long n, uint8_t base) { char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. char *str = &buf[sizeof(buf) - 1]; *str = '\0'; 720: 19 a2 std Y+33, r1 ; 0x21 722: 8e 01 movw r16, r28 724: 0f 5d subi r16, 0xDF ; 223 726: 1f 4f sbci r17, 0xFF ; 255 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; n /= base; 728: ca 01 movw r24, r20 72a: b9 01 movw r22, r18 72c: a5 01 movw r20, r10 72e: 94 01 movw r18, r8 730: 0e 94 1c 04 call 0x838 ; 0x838 <__udivmodsi4> *--str = c < 10 ? c + '0' : c + 'A' - 10; 734: 60 5d subi r22, 0xD0 ; 208 736: f8 01 movw r30, r16 738: 62 93 st -Z, r22 73a: 8f 01 movw r16, r30 *str = '\0'; // prevent crash if called with base == 1 if (base < 2) base = 10; do { 73c: 21 15 cp r18, r1 73e: 31 05 cpc r19, r1 740: 41 05 cpc r20, r1 742: 51 05 cpc r21, r1 744: 89 f7 brne .-30 ; 0x728 746: 15 c0 rjmp .+42 ; 0x772 if (n < 0) { int t = print('-'); n = -n; return printNumber(n, 10) + t; } return printNumber(n, 10); 748: a7 01 movw r20, r14 74a: 96 01 movw r18, r12 size_t Print::printNumber(unsigned long n, uint8_t base) { char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. char *str = &buf[sizeof(buf) - 1]; *str = '\0'; 74c: 19 a2 std Y+33, r1 ; 0x21 74e: 8e 01 movw r16, r28 750: 0f 5d subi r16, 0xDF ; 223 752: 1f 4f sbci r17, 0xFF ; 255 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; n /= base; 754: ca 01 movw r24, r20 756: b9 01 movw r22, r18 758: a5 01 movw r20, r10 75a: 94 01 movw r18, r8 75c: 0e 94 1c 04 call 0x838 ; 0x838 <__udivmodsi4> *--str = c < 10 ? c + '0' : c + 'A' - 10; 760: 60 5d subi r22, 0xD0 ; 208 762: f8 01 movw r30, r16 764: 62 93 st -Z, r22 766: 8f 01 movw r16, r30 *str = '\0'; // prevent crash if called with base == 1 if (base < 2) base = 10; do { 768: 21 15 cp r18, r1 76a: 31 05 cpc r19, r1 76c: 41 05 cpc r20, r1 76e: 51 05 cpc r21, r1 770: 89 f7 brne .-30 ; 0x754 n /= base; *--str = c < 10 ? c + '0' : c + 'A' - 10; } while(n); return write(str); 772: c8 01 movw r24, r16 774: 0e 94 ac 01 call 0x358 ; 0x358 <_ZN5Print5writeEPKc.constprop.13> return write(s.c_str(), s.length()); } size_t Print::print(const char str[]) { return write(str); 778: 82 e1 ldi r24, 0x12 ; 18 77a: 91 e0 ldi r25, 0x01 ; 1 77c: 0e 94 ac 01 call 0x358 ; 0x358 <_ZN5Print5writeEPKc.constprop.13> return x.printTo(*this); } size_t Print::println(void) { return write("\r\n"); 780: 86 e1 ldi r24, 0x16 ; 22 782: 91 e0 ldi r25, 0x01 ; 1 784: 0e 94 ac 01 call 0x358 ; 0x358 <_ZN5Print5writeEPKc.constprop.13> Serial.print("us "); Serial.println(); newVal=false; 788: 10 92 2f 01 sts 0x012F, r1 return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond()); } void delay(unsigned long ms) { uint32_t start = micros(); 78c: 0e 94 87 01 call 0x30e ; 0x30e 790: 2b 01 movw r4, r22 792: 3c 01 movw r6, r24 794: 84 e6 ldi r24, 0x64 ; 100 796: c8 2e mov r12, r24 798: d1 2c mov r13, r1 79a: e1 2c mov r14, r1 79c: f1 2c mov r15, r1 while (ms > 0) { yield(); while ( ms > 0 && (micros() - start) >= 1000) { 79e: 0e 94 87 01 call 0x30e ; 0x30e 7a2: dc 01 movw r26, r24 7a4: cb 01 movw r24, r22 7a6: 84 19 sub r24, r4 7a8: 95 09 sbc r25, r5 7aa: a6 09 sbc r26, r6 7ac: b7 09 sbc r27, r7 7ae: 88 3e cpi r24, 0xE8 ; 232 7b0: 93 40 sbci r25, 0x03 ; 3 7b2: a1 05 cpc r26, r1 7b4: b1 05 cpc r27, r1 7b6: 58 f0 brcs .+22 ; 0x7ce ms--; 7b8: f1 e0 ldi r31, 0x01 ; 1 7ba: cf 1a sub r12, r31 7bc: d1 08 sbc r13, r1 7be: e1 08 sbc r14, r1 7c0: f1 08 sbc r15, r1 start += 1000; 7c2: 28 ee ldi r18, 0xE8 ; 232 7c4: 42 0e add r4, r18 7c6: 23 e0 ldi r18, 0x03 ; 3 7c8: 52 1e adc r5, r18 7ca: 61 1c adc r6, r1 7cc: 71 1c adc r7, r1 { uint32_t start = micros(); while (ms > 0) { yield(); while ( ms > 0 && (micros() - start) >= 1000) { 7ce: c1 14 cp r12, r1 7d0: d1 04 cpc r13, r1 7d2: e1 04 cpc r14, r1 7d4: f1 04 cpc r15, r1 7d6: 19 f7 brne .-58 ; 0x79e setup(); for (;;) { loop(); if (serialEventRun) serialEventRun(); 7d8: 0e 94 7d 01 call 0x2fa ; 0x2fa <_Z14serialEventRunv> 7dc: 80 cf rjmp .-256 ; 0x6de 000007de <_GLOBAL__sub_I___vector_18>: size_t printNumber(unsigned long, uint8_t); size_t printFloat(double, uint8_t); protected: void setWriteError(int err = 1) { write_error = err; } public: Print() : write_error(0) {} 7de: e0 e3 ldi r30, 0x30 ; 48 7e0: f1 e0 ldi r31, 0x01 ; 1 7e2: 13 82 std Z+3, r1 ; 0x03 7e4: 12 82 std Z+2, r1 ; 0x02 public: virtual int available() = 0; virtual int read() = 0; virtual int peek() = 0; Stream() {_timeout=1000;} 7e6: 88 ee ldi r24, 0xE8 ; 232 7e8: 93 e0 ldi r25, 0x03 ; 3 7ea: a0 e0 ldi r26, 0x00 ; 0 7ec: b0 e0 ldi r27, 0x00 ; 0 7ee: 84 83 std Z+4, r24 ; 0x04 7f0: 95 83 std Z+5, r25 ; 0x05 7f2: a6 83 std Z+6, r26 ; 0x06 7f4: b7 83 std Z+7, r27 ; 0x07 volatile uint8_t *ucsrc, volatile uint8_t *udr) : _ubrrh(ubrrh), _ubrrl(ubrrl), _ucsra(ucsra), _ucsrb(ucsrb), _ucsrc(ucsrc), _udr(udr), _rx_buffer_head(0), _rx_buffer_tail(0), _tx_buffer_head(0), _tx_buffer_tail(0) 7f6: 84 e0 ldi r24, 0x04 ; 4 7f8: 91 e0 ldi r25, 0x01 ; 1 7fa: 91 83 std Z+1, r25 ; 0x01 7fc: 80 83 st Z, r24 7fe: 85 ec ldi r24, 0xC5 ; 197 800: 90 e0 ldi r25, 0x00 ; 0 802: 95 87 std Z+13, r25 ; 0x0d 804: 84 87 std Z+12, r24 ; 0x0c 806: 84 ec ldi r24, 0xC4 ; 196 808: 90 e0 ldi r25, 0x00 ; 0 80a: 97 87 std Z+15, r25 ; 0x0f 80c: 86 87 std Z+14, r24 ; 0x0e 80e: 80 ec ldi r24, 0xC0 ; 192 810: 90 e0 ldi r25, 0x00 ; 0 812: 91 8b std Z+17, r25 ; 0x11 814: 80 8b std Z+16, r24 ; 0x10 816: 81 ec ldi r24, 0xC1 ; 193 818: 90 e0 ldi r25, 0x00 ; 0 81a: 93 8b std Z+19, r25 ; 0x13 81c: 82 8b std Z+18, r24 ; 0x12 81e: 82 ec ldi r24, 0xC2 ; 194 820: 90 e0 ldi r25, 0x00 ; 0 822: 95 8b std Z+21, r25 ; 0x15 824: 84 8b std Z+20, r24 ; 0x14 826: 86 ec ldi r24, 0xC6 ; 198 828: 90 e0 ldi r25, 0x00 ; 0 82a: 97 8b std Z+23, r25 ; 0x17 82c: 86 8b std Z+22, r24 ; 0x16 82e: 11 8e std Z+25, r1 ; 0x19 830: 12 8e std Z+26, r1 ; 0x1a 832: 13 8e std Z+27, r1 ; 0x1b 834: 14 8e std Z+28, r1 ; 0x1c 836: 08 95 ret 00000838 <__udivmodsi4>: 838: a1 e2 ldi r26, 0x21 ; 33 83a: 1a 2e mov r1, r26 83c: aa 1b sub r26, r26 83e: bb 1b sub r27, r27 840: fd 01 movw r30, r26 842: 0d c0 rjmp .+26 ; 0x85e <__udivmodsi4_ep> 00000844 <__udivmodsi4_loop>: 844: aa 1f adc r26, r26 846: bb 1f adc r27, r27 848: ee 1f adc r30, r30 84a: ff 1f adc r31, r31 84c: a2 17 cp r26, r18 84e: b3 07 cpc r27, r19 850: e4 07 cpc r30, r20 852: f5 07 cpc r31, r21 854: 20 f0 brcs .+8 ; 0x85e <__udivmodsi4_ep> 856: a2 1b sub r26, r18 858: b3 0b sbc r27, r19 85a: e4 0b sbc r30, r20 85c: f5 0b sbc r31, r21 0000085e <__udivmodsi4_ep>: 85e: 66 1f adc r22, r22 860: 77 1f adc r23, r23 862: 88 1f adc r24, r24 864: 99 1f adc r25, r25 866: 1a 94 dec r1 868: 69 f7 brne .-38 ; 0x844 <__udivmodsi4_loop> 86a: 60 95 com r22 86c: 70 95 com r23 86e: 80 95 com r24 870: 90 95 com r25 872: 9b 01 movw r18, r22 874: ac 01 movw r20, r24 876: bd 01 movw r22, r26 878: cf 01 movw r24, r30 87a: 08 95 ret 0000087c <__tablejump2__>: 87c: ee 0f add r30, r30 87e: ff 1f adc r31, r31 880: 05 90 lpm r0, Z+ 882: f4 91 lpm r31, Z 884: e0 2d mov r30, r0 886: 09 94 ijmp 00000888 : 888: 81 e0 ldi r24, 0x01 ; 1 88a: 90 e0 ldi r25, 0x00 ; 0 88c: f8 94 cli 88e: 0c 94 49 04 jmp 0x892 ; 0x892 <_exit> 00000892 <_exit>: 892: f8 94 cli 00000894 <__stop_program>: 894: ff cf rjmp .-2 ; 0x894 <__stop_program>