PulseWidthInt.ino.elf: file format elf32-avr Disassembly of section .text: 00000000 <__vectors>: 0: 0c 94 62 00 jmp 0xc4 ; 0xc4 <__ctors_end> 4: 0c 94 22 03 jmp 0x644 ; 0x644 <__vector_1> 8: 0c 94 fb 02 jmp 0x5f6 ; 0x5f6 <__vector_2> c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 10: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 14: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 18: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 1c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 20: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 24: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 28: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 2c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 30: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 34: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 38: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 3c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 40: 0c 94 b1 02 jmp 0x562 ; 0x562 <__vector_16> 44: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 48: 0c 94 7f 02 jmp 0x4fe ; 0x4fe <__vector_18> 4c: 0c 94 59 02 jmp 0x4b2 ; 0x4b2 <__vector_19> 50: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 54: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 58: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 5c: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 60: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 64: 0c 94 8a 00 jmp 0x114 ; 0x114 <__bad_interrupt> 00000068 <__trampolines_end>: 68: 00 00 nop 6a: 00 00 nop 6c: 23 00 .word 0x0023 ; ???? 6e: 26 00 .word 0x0026 ; ???? 70: 29 00 .word 0x0029 ; ???? 00000072 : 72: 00 00 00 08 00 02 01 00 00 03 04 07 00 00 00 00 ................ 82: 00 00 00 00 .... 00000086 : 86: 00 00 00 00 25 00 28 00 2b 00 ....%.(.+. 00000090 : 90: 00 00 00 00 24 00 27 00 2a 00 ....$.'.*. 0000009a : 9a: 04 04 04 04 04 04 04 04 02 02 02 02 02 02 03 03 ................ aa: 03 03 03 03 .... 000000ae : ae: 01 02 04 08 10 20 40 80 01 02 04 08 10 20 01 02 ..... @...... .. be: 04 08 10 20 ... 000000c2 <__ctors_start>: c2: 75 04 cpc r7, r5 000000c4 <__ctors_end>: c4: 11 24 eor r1, r1 c6: 1f be out 0x3f, r1 ; 63 c8: cf ef ldi r28, 0xFF ; 255 ca: d8 e0 ldi r29, 0x08 ; 8 cc: de bf out 0x3e, r29 ; 62 ce: cd bf out 0x3d, r28 ; 61 000000d0 <__do_copy_data>: d0: 11 e0 ldi r17, 0x01 ; 1 d2: a0 e0 ldi r26, 0x00 ; 0 d4: b1 e0 ldi r27, 0x01 ; 1 d6: e2 ea ldi r30, 0xA2 ; 162 d8: f9 e0 ldi r31, 0x09 ; 9 da: 02 c0 rjmp .+4 ; 0xe0 <__do_copy_data+0x10> dc: 05 90 lpm r0, Z+ de: 0d 92 st X+, r0 e0: ae 31 cpi r26, 0x1E ; 30 e2: b1 07 cpc r27, r17 e4: d9 f7 brne .-10 ; 0xdc <__do_copy_data+0xc> 000000e6 <__do_clear_bss>: e6: 21 e0 ldi r18, 0x01 ; 1 e8: ae e1 ldi r26, 0x1E ; 30 ea: b1 e0 ldi r27, 0x01 ; 1 ec: 01 c0 rjmp .+2 ; 0xf0 <.do_clear_bss_start> 000000ee <.do_clear_bss_loop>: ee: 1d 92 st X+, r1 000000f0 <.do_clear_bss_start>: f0: a1 3d cpi r26, 0xD1 ; 209 f2: b2 07 cpc r27, r18 f4: e1 f7 brne .-8 ; 0xee <.do_clear_bss_loop> 000000f6 <__do_global_ctors>: f6: 10 e0 ldi r17, 0x00 ; 0 f8: c2 e6 ldi r28, 0x62 ; 98 fa: d0 e0 ldi r29, 0x00 ; 0 fc: 04 c0 rjmp .+8 ; 0x106 <__do_global_ctors+0x10> fe: 21 97 sbiw r28, 0x01 ; 1 100: fe 01 movw r30, r28 102: 0e 94 c4 04 call 0x988 ; 0x988 <__tablejump2__> 106: c1 36 cpi r28, 0x61 ; 97 108: d1 07 cpc r29, r17 10a: c9 f7 brne .-14 ; 0xfe <__do_global_ctors+0x8> 10c: 0e 94 49 03 call 0x692 ; 0x692
110: 0c 94 cf 04 jmp 0x99e ; 0x99e <_exit> 00000114 <__bad_interrupt>: 114: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 00000118 <_ZN5Print5writeEPKhj>: // Public Methods ////////////////////////////////////////////////////////////// /* default implementation: may be overridden */ size_t Print::write(const uint8_t *buffer, size_t size) { 118: cf 92 push r12 11a: df 92 push r13 11c: ef 92 push r14 11e: ff 92 push r15 120: 0f 93 push r16 122: 1f 93 push r17 124: cf 93 push r28 126: df 93 push r29 128: 6c 01 movw r12, r24 12a: 7a 01 movw r14, r20 12c: 8b 01 movw r16, r22 size_t n = 0; 12e: c0 e0 ldi r28, 0x00 ; 0 130: d0 e0 ldi r29, 0x00 ; 0 while (size--) { 132: ce 15 cp r28, r14 134: df 05 cpc r29, r15 136: 89 f0 breq .+34 ; 0x15a <_ZN5Print5writeEPKhj+0x42> if (write(*buffer++)) n++; 138: d8 01 movw r26, r16 13a: 6d 91 ld r22, X+ 13c: 8d 01 movw r16, r26 13e: d6 01 movw r26, r12 140: ed 91 ld r30, X+ 142: fc 91 ld r31, X 144: 01 90 ld r0, Z+ 146: f0 81 ld r31, Z 148: e0 2d mov r30, r0 14a: c6 01 movw r24, r12 14c: 09 95 icall 14e: 89 2b or r24, r25 150: 11 f4 brne .+4 ; 0x156 <_ZN5Print5writeEPKhj+0x3e> 152: 7e 01 movw r14, r28 154: 02 c0 rjmp .+4 ; 0x15a <_ZN5Print5writeEPKhj+0x42> 156: 21 96 adiw r28, 0x01 ; 1 158: ec cf rjmp .-40 ; 0x132 <_ZN5Print5writeEPKhj+0x1a> else break; } return n; } 15a: c7 01 movw r24, r14 15c: df 91 pop r29 15e: cf 91 pop r28 160: 1f 91 pop r17 162: 0f 91 pop r16 164: ff 90 pop r15 166: ef 90 pop r14 168: df 90 pop r13 16a: cf 90 pop r12 16c: 08 95 ret 0000016e <_ZN5Print5flushEv>: size_t println(unsigned long, int = DEC); size_t println(double, int = 2); size_t println(const Printable&); size_t println(void); virtual void flush() { /* Empty implementation for backward compatibility */ } 16e: 08 95 ret 00000170 <_ZN5Print17availableForWriteEv>: return write((const uint8_t *)buffer, size); } // default to zero, meaning "a single write may block" // should be overriden by subclasses with buffering virtual int availableForWrite() { return 0; } 170: 80 e0 ldi r24, 0x00 ; 0 172: 90 e0 ldi r25, 0x00 ; 0 174: 08 95 ret 00000176 <_ZN14HardwareSerial17availableForWriteEv>: { #if (SERIAL_TX_BUFFER_SIZE>256) uint8_t oldSREG = SREG; cli(); #endif tx_buffer_index_t head = _tx_buffer_head; 176: fc 01 movw r30, r24 178: 53 8d ldd r21, Z+27 ; 0x1b tx_buffer_index_t tail = _tx_buffer_tail; 17a: 44 8d ldd r20, Z+28 ; 0x1c 17c: 25 2f mov r18, r21 17e: 30 e0 ldi r19, 0x00 ; 0 180: 84 2f mov r24, r20 182: 90 e0 ldi r25, 0x00 ; 0 #if (SERIAL_TX_BUFFER_SIZE>256) SREG = oldSREG; #endif if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail; 184: 82 1b sub r24, r18 186: 93 0b sbc r25, r19 188: 54 17 cp r21, r20 18a: 10 f0 brcs .+4 ; 0x190 <_ZN14HardwareSerial17availableForWriteEv+0x1a> 18c: cf 96 adiw r24, 0x3f ; 63 18e: 08 95 ret return tail - head - 1; 190: 01 97 sbiw r24, 0x01 ; 1 } 192: 08 95 ret 00000194 <_ZN14HardwareSerial4readEv>: return _rx_buffer[_rx_buffer_tail]; } } int HardwareSerial::read(void) { 194: fc 01 movw r30, r24 // if the head isn't ahead of the tail, we don't have any characters if (_rx_buffer_head == _rx_buffer_tail) { 196: 91 8d ldd r25, Z+25 ; 0x19 198: 82 8d ldd r24, Z+26 ; 0x1a 19a: 98 17 cp r25, r24 19c: 61 f0 breq .+24 ; 0x1b6 <_ZN14HardwareSerial4readEv+0x22> return -1; } else { unsigned char c = _rx_buffer[_rx_buffer_tail]; 19e: 82 8d ldd r24, Z+26 ; 0x1a 1a0: df 01 movw r26, r30 1a2: a8 0f add r26, r24 1a4: b1 1d adc r27, r1 1a6: 5d 96 adiw r26, 0x1d ; 29 1a8: 8c 91 ld r24, X _rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE; 1aa: 92 8d ldd r25, Z+26 ; 0x1a 1ac: 9f 5f subi r25, 0xFF ; 255 1ae: 9f 73 andi r25, 0x3F ; 63 1b0: 92 8f std Z+26, r25 ; 0x1a return c; 1b2: 90 e0 ldi r25, 0x00 ; 0 1b4: 08 95 ret int HardwareSerial::read(void) { // if the head isn't ahead of the tail, we don't have any characters if (_rx_buffer_head == _rx_buffer_tail) { return -1; 1b6: 8f ef ldi r24, 0xFF ; 255 1b8: 9f ef ldi r25, 0xFF ; 255 } else { unsigned char c = _rx_buffer[_rx_buffer_tail]; _rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE; return c; } } 1ba: 08 95 ret 000001bc <_ZN14HardwareSerial4peekEv>: { return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE; } int HardwareSerial::peek(void) { 1bc: fc 01 movw r30, r24 if (_rx_buffer_head == _rx_buffer_tail) { 1be: 91 8d ldd r25, Z+25 ; 0x19 1c0: 82 8d ldd r24, Z+26 ; 0x1a 1c2: 98 17 cp r25, r24 1c4: 31 f0 breq .+12 ; 0x1d2 <_ZN14HardwareSerial4peekEv+0x16> return -1; } else { return _rx_buffer[_rx_buffer_tail]; 1c6: 82 8d ldd r24, Z+26 ; 0x1a 1c8: e8 0f add r30, r24 1ca: f1 1d adc r31, r1 1cc: 85 8d ldd r24, Z+29 ; 0x1d 1ce: 90 e0 ldi r25, 0x00 ; 0 1d0: 08 95 ret } int HardwareSerial::peek(void) { if (_rx_buffer_head == _rx_buffer_tail) { return -1; 1d2: 8f ef ldi r24, 0xFF ; 255 1d4: 9f ef ldi r25, 0xFF ; 255 } else { return _rx_buffer[_rx_buffer_tail]; } } 1d6: 08 95 ret 000001d8 <_ZN14HardwareSerial9availableEv>: // clear any received data _rx_buffer_head = _rx_buffer_tail; } int HardwareSerial::available(void) { 1d8: fc 01 movw r30, r24 return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE; 1da: 91 8d ldd r25, Z+25 ; 0x19 1dc: 22 8d ldd r18, Z+26 ; 0x1a 1de: 89 2f mov r24, r25 1e0: 90 e0 ldi r25, 0x00 ; 0 1e2: 80 5c subi r24, 0xC0 ; 192 1e4: 9f 4f sbci r25, 0xFF ; 255 1e6: 82 1b sub r24, r18 1e8: 91 09 sbc r25, r1 } 1ea: 8f 73 andi r24, 0x3F ; 63 1ec: 99 27 eor r25, r25 1ee: 08 95 ret 000001f0 <_Z17Serial0_availablev>: #endif // Function that can be weakly referenced by serialEventRun to prevent // pulling in this file if it's not otherwise used. bool Serial0_available() { return Serial.available(); 1f0: 84 e3 ldi r24, 0x34 ; 52 1f2: 91 e0 ldi r25, 0x01 ; 1 1f4: 0e 94 ec 00 call 0x1d8 ; 0x1d8 <_ZN14HardwareSerial9availableEv> 1f8: 21 e0 ldi r18, 0x01 ; 1 1fa: 89 2b or r24, r25 1fc: 09 f4 brne .+2 ; 0x200 <_Z17Serial0_availablev+0x10> 1fe: 20 e0 ldi r18, 0x00 ; 0 } 200: 82 2f mov r24, r18 202: 08 95 ret 00000204 <_ZN14HardwareSerial17_tx_udr_empty_irqEv>: } // Actual interrupt handlers ////////////////////////////////////////////////////////////// void HardwareSerial::_tx_udr_empty_irq(void) { 204: fc 01 movw r30, r24 // If interrupts are enabled, there must be more data in the output // buffer. Send the next byte unsigned char c = _tx_buffer[_tx_buffer_tail]; 206: 84 8d ldd r24, Z+28 ; 0x1c 208: df 01 movw r26, r30 20a: a8 0f add r26, r24 20c: b1 1d adc r27, r1 20e: a3 5a subi r26, 0xA3 ; 163 210: bf 4f sbci r27, 0xFF ; 255 212: 2c 91 ld r18, X _tx_buffer_tail = (_tx_buffer_tail + 1) % SERIAL_TX_BUFFER_SIZE; 214: 84 8d ldd r24, Z+28 ; 0x1c 216: 90 e0 ldi r25, 0x00 ; 0 218: 01 96 adiw r24, 0x01 ; 1 21a: 8f 73 andi r24, 0x3F ; 63 21c: 99 27 eor r25, r25 21e: 84 8f std Z+28, r24 ; 0x1c *_udr = c; 220: a6 89 ldd r26, Z+22 ; 0x16 222: b7 89 ldd r27, Z+23 ; 0x17 224: 2c 93 st X, r18 // clear the TXC bit -- "can be cleared by writing a one to its bit // location". This makes sure flush() won't return until the bytes // actually got written sbi(*_ucsra, TXC0); 226: a0 89 ldd r26, Z+16 ; 0x10 228: b1 89 ldd r27, Z+17 ; 0x11 22a: 8c 91 ld r24, X 22c: 80 64 ori r24, 0x40 ; 64 22e: 8c 93 st X, r24 if (_tx_buffer_head == _tx_buffer_tail) { 230: 93 8d ldd r25, Z+27 ; 0x1b 232: 84 8d ldd r24, Z+28 ; 0x1c 234: 98 13 cpse r25, r24 236: 06 c0 rjmp .+12 ; 0x244 <_ZN14HardwareSerial17_tx_udr_empty_irqEv+0x40> // Buffer empty, so disable interrupts cbi(*_ucsrb, UDRIE0); 238: 02 88 ldd r0, Z+18 ; 0x12 23a: f3 89 ldd r31, Z+19 ; 0x13 23c: e0 2d mov r30, r0 23e: 80 81 ld r24, Z 240: 8f 7d andi r24, 0xDF ; 223 242: 80 83 st Z, r24 244: 08 95 ret 00000246 <_ZN14HardwareSerial5writeEh>: // If we get here, nothing is queued anymore (DRIE is disabled) and // the hardware finished tranmission (TXC is set). } size_t HardwareSerial::write(uint8_t c) { 246: ef 92 push r14 248: ff 92 push r15 24a: 0f 93 push r16 24c: 1f 93 push r17 24e: cf 93 push r28 250: df 93 push r29 252: ec 01 movw r28, r24 _written = true; 254: 81 e0 ldi r24, 0x01 ; 1 256: 88 8f std Y+24, r24 ; 0x18 // If the buffer and the data register is empty, just write the byte // to the data register and be done. This shortcut helps // significantly improve the effective datarate at high (> // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { 258: 9b 8d ldd r25, Y+27 ; 0x1b 25a: 8c 8d ldd r24, Y+28 ; 0x1c 25c: 98 13 cpse r25, r24 25e: 05 c0 rjmp .+10 ; 0x26a <_ZN14HardwareSerial5writeEh+0x24> 260: e8 89 ldd r30, Y+16 ; 0x10 262: f9 89 ldd r31, Y+17 ; 0x11 264: 80 81 ld r24, Z 266: 85 fd sbrc r24, 5 268: 24 c0 rjmp .+72 ; 0x2b2 <_ZN14HardwareSerial5writeEh+0x6c> 26a: f6 2e mov r15, r22 *_udr = c; sbi(*_ucsra, TXC0); return 1; } tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE; 26c: 0b 8d ldd r16, Y+27 ; 0x1b 26e: 10 e0 ldi r17, 0x00 ; 0 270: 0f 5f subi r16, 0xFF ; 255 272: 1f 4f sbci r17, 0xFF ; 255 274: 0f 73 andi r16, 0x3F ; 63 276: 11 27 eor r17, r17 278: e0 2e mov r14, r16 // If the output buffer is full, there's nothing for it other than to // wait for the interrupt handler to empty it a bit while (i == _tx_buffer_tail) { 27a: 8c 8d ldd r24, Y+28 ; 0x1c 27c: e8 12 cpse r14, r24 27e: 0c c0 rjmp .+24 ; 0x298 <_ZN14HardwareSerial5writeEh+0x52> if (bit_is_clear(SREG, SREG_I)) { 280: 0f b6 in r0, 0x3f ; 63 282: 07 fc sbrc r0, 7 284: fa cf rjmp .-12 ; 0x27a <_ZN14HardwareSerial5writeEh+0x34> // Interrupts are disabled, so we'll have to poll the data // register empty flag ourselves. If it is set, pretend an // interrupt has happened and call the handler to free up // space for us. if(bit_is_set(*_ucsra, UDRE0)) 286: e8 89 ldd r30, Y+16 ; 0x10 288: f9 89 ldd r31, Y+17 ; 0x11 28a: 80 81 ld r24, Z 28c: 85 ff sbrs r24, 5 28e: f5 cf rjmp .-22 ; 0x27a <_ZN14HardwareSerial5writeEh+0x34> _tx_udr_empty_irq(); 290: ce 01 movw r24, r28 292: 0e 94 02 01 call 0x204 ; 0x204 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> 296: f1 cf rjmp .-30 ; 0x27a <_ZN14HardwareSerial5writeEh+0x34> } else { // nop, the interrupt handler will free up space for us } } _tx_buffer[_tx_buffer_head] = c; 298: 8b 8d ldd r24, Y+27 ; 0x1b 29a: fe 01 movw r30, r28 29c: e8 0f add r30, r24 29e: f1 1d adc r31, r1 2a0: e3 5a subi r30, 0xA3 ; 163 2a2: ff 4f sbci r31, 0xFF ; 255 2a4: f0 82 st Z, r15 _tx_buffer_head = i; 2a6: 0b 8f std Y+27, r16 ; 0x1b sbi(*_ucsrb, UDRIE0); 2a8: ea 89 ldd r30, Y+18 ; 0x12 2aa: fb 89 ldd r31, Y+19 ; 0x13 2ac: 80 81 ld r24, Z 2ae: 80 62 ori r24, 0x20 ; 32 2b0: 07 c0 rjmp .+14 ; 0x2c0 <_ZN14HardwareSerial5writeEh+0x7a> // If the buffer and the data register is empty, just write the byte // to the data register and be done. This shortcut helps // significantly improve the effective datarate at high (> // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { *_udr = c; 2b2: ee 89 ldd r30, Y+22 ; 0x16 2b4: ff 89 ldd r31, Y+23 ; 0x17 2b6: 60 83 st Z, r22 sbi(*_ucsra, TXC0); 2b8: e8 89 ldd r30, Y+16 ; 0x10 2ba: f9 89 ldd r31, Y+17 ; 0x11 2bc: 80 81 ld r24, Z 2be: 80 64 ori r24, 0x40 ; 64 2c0: 80 83 st Z, r24 _tx_buffer_head = i; sbi(*_ucsrb, UDRIE0); return 1; } 2c2: 81 e0 ldi r24, 0x01 ; 1 2c4: 90 e0 ldi r25, 0x00 ; 0 2c6: df 91 pop r29 2c8: cf 91 pop r28 2ca: 1f 91 pop r17 2cc: 0f 91 pop r16 2ce: ff 90 pop r15 2d0: ef 90 pop r14 2d2: 08 95 ret 000002d4 <_ZN14HardwareSerial5flushEv>: if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail; return tail - head - 1; } void HardwareSerial::flush() { 2d4: cf 93 push r28 2d6: df 93 push r29 2d8: ec 01 movw r28, r24 // If we have never written a byte, no need to flush. This special // case is needed since there is no way to force the TXC (transmit // complete) bit to 1 during initialization if (!_written) 2da: 88 8d ldd r24, Y+24 ; 0x18 2dc: 88 23 and r24, r24 2de: c9 f0 breq .+50 ; 0x312 <_ZN14HardwareSerial5flushEv+0x3e> return; while (bit_is_set(*_ucsrb, UDRIE0) || bit_is_clear(*_ucsra, TXC0)) { 2e0: ea 89 ldd r30, Y+18 ; 0x12 2e2: fb 89 ldd r31, Y+19 ; 0x13 2e4: 80 81 ld r24, Z 2e6: 85 fd sbrc r24, 5 2e8: 05 c0 rjmp .+10 ; 0x2f4 <_ZN14HardwareSerial5flushEv+0x20> 2ea: a8 89 ldd r26, Y+16 ; 0x10 2ec: b9 89 ldd r27, Y+17 ; 0x11 2ee: 8c 91 ld r24, X 2f0: 86 fd sbrc r24, 6 2f2: 0f c0 rjmp .+30 ; 0x312 <_ZN14HardwareSerial5flushEv+0x3e> if (bit_is_clear(SREG, SREG_I) && bit_is_set(*_ucsrb, UDRIE0)) 2f4: 0f b6 in r0, 0x3f ; 63 2f6: 07 fc sbrc r0, 7 2f8: f5 cf rjmp .-22 ; 0x2e4 <_ZN14HardwareSerial5flushEv+0x10> 2fa: 80 81 ld r24, Z 2fc: 85 ff sbrs r24, 5 2fe: f2 cf rjmp .-28 ; 0x2e4 <_ZN14HardwareSerial5flushEv+0x10> // Interrupts are globally disabled, but the DR empty // interrupt should be enabled, so poll the DR empty flag to // prevent deadlock if (bit_is_set(*_ucsra, UDRE0)) 300: a8 89 ldd r26, Y+16 ; 0x10 302: b9 89 ldd r27, Y+17 ; 0x11 304: 8c 91 ld r24, X 306: 85 ff sbrs r24, 5 308: ed cf rjmp .-38 ; 0x2e4 <_ZN14HardwareSerial5flushEv+0x10> _tx_udr_empty_irq(); 30a: ce 01 movw r24, r28 30c: 0e 94 02 01 call 0x204 ; 0x204 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> 310: e7 cf rjmp .-50 ; 0x2e0 <_ZN14HardwareSerial5flushEv+0xc> } // If we get here, nothing is queued anymore (DRIE is disabled) and // the hardware finished tranmission (TXC is set). } 312: df 91 pop r29 314: cf 91 pop r28 316: 08 95 ret 00000318 <_Z14serialEventRunv>: #endif void serialEventRun(void) { #if defined(HAVE_HWSERIAL0) if (Serial0_available && serialEvent && Serial0_available()) serialEvent(); 318: 80 e0 ldi r24, 0x00 ; 0 31a: 90 e0 ldi r25, 0x00 ; 0 31c: 89 2b or r24, r25 31e: 29 f0 breq .+10 ; 0x32a <_Z14serialEventRunv+0x12> 320: 0e 94 f8 00 call 0x1f0 ; 0x1f0 <_Z17Serial0_availablev> 324: 81 11 cpse r24, r1 326: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 32a: 08 95 ret 0000032c : return m; } unsigned long micros() { unsigned long m; uint8_t oldSREG = SREG, t; 32c: 3f b7 in r19, 0x3f ; 63 cli(); 32e: f8 94 cli m = timer0_overflow_count; 330: 80 91 2b 01 lds r24, 0x012B 334: 90 91 2c 01 lds r25, 0x012C 338: a0 91 2d 01 lds r26, 0x012D 33c: b0 91 2e 01 lds r27, 0x012E #if defined(TCNT0) t = TCNT0; 340: 26 b5 in r18, 0x26 ; 38 #else #error TIMER 0 not defined #endif #ifdef TIFR0 if ((TIFR0 & _BV(TOV0)) && (t < 255)) 342: a8 9b sbis 0x15, 0 ; 21 344: 05 c0 rjmp .+10 ; 0x350 346: 2f 3f cpi r18, 0xFF ; 255 348: 19 f0 breq .+6 ; 0x350 m++; 34a: 01 96 adiw r24, 0x01 ; 1 34c: a1 1d adc r26, r1 34e: b1 1d adc r27, r1 #else if ((TIFR & _BV(TOV0)) && (t < 255)) m++; #endif SREG = oldSREG; 350: 3f bf out 0x3f, r19 ; 63 return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond()); 352: ba 2f mov r27, r26 354: a9 2f mov r26, r25 356: 98 2f mov r25, r24 358: 88 27 eor r24, r24 35a: 82 0f add r24, r18 35c: 91 1d adc r25, r1 35e: a1 1d adc r26, r1 360: b1 1d adc r27, r1 362: bc 01 movw r22, r24 364: cd 01 movw r24, r26 366: 42 e0 ldi r20, 0x02 ; 2 368: 66 0f add r22, r22 36a: 77 1f adc r23, r23 36c: 88 1f adc r24, r24 36e: 99 1f adc r25, r25 370: 4a 95 dec r20 372: d1 f7 brne .-12 ; 0x368 } 374: 08 95 ret 00000376 : #include #include #include "wiring_private.h" static void nothing(void) { 376: 08 95 ret 00000378 : }; // volatile static voidFuncPtr twiIntFunc; void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode) { if(interruptNum < EXTERNAL_NUM_INTERRUPTS) { intFunc[interruptNum] = userFunc; 378: 2a ec ldi r18, 0xCA ; 202 37a: 31 e0 ldi r19, 0x01 ; 1 37c: 30 93 01 01 sts 0x0101, r19 380: 20 93 00 01 sts 0x0100, r18 EIMSK |= (1 << INT7); break; #else case 0: #if defined(EICRA) && defined(ISC00) && defined(EIMSK) EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00); 384: e9 e6 ldi r30, 0x69 ; 105 386: f0 e0 ldi r31, 0x00 ; 0 388: 90 81 ld r25, Z 38a: 9c 7f andi r25, 0xFC ; 252 38c: 89 2b or r24, r25 38e: 80 83 st Z, r24 EIMSK |= (1 << INT0); 390: e8 9a sbi 0x1d, 0 ; 29 392: 08 95 ret 00000394 <_Z4ISR0v>: SREG = oldSREG; } int digitalRead(uint8_t pin) { uint8_t timer = digitalPinToTimer(pin); 394: e4 e7 ldi r30, 0x74 ; 116 396: f0 e0 ldi r31, 0x00 ; 0 398: 84 91 lpm r24, Z uint8_t bit = digitalPinToBitMask(pin); 39a: e0 eb ldi r30, 0xB0 ; 176 39c: f0 e0 ldi r31, 0x00 ; 0 39e: 94 91 lpm r25, Z uint8_t port = digitalPinToPort(pin); 3a0: ec e9 ldi r30, 0x9C ; 156 3a2: f0 e0 ldi r31, 0x00 ; 0 3a4: e4 91 lpm r30, Z if (port == NOT_A_PIN) return LOW; 3a6: ee 23 and r30, r30 3a8: 09 f4 brne .+2 ; 0x3ac <_Z4ISR0v+0x18> 3aa: 41 c0 rjmp .+130 ; 0x42e <__LOCK_REGION_LENGTH__+0x2e> // If the pin that support PWM output, we need to turn it off // before getting a digital reading. if (timer != NOT_ON_TIMER) turnOffPWM(timer); 3ac: 88 23 and r24, r24 3ae: 39 f1 breq .+78 ; 0x3fe <_Z4ISR0v+0x6a> // //static inline void turnOffPWM(uint8_t timer) __attribute__ ((always_inline)); //static inline void turnOffPWM(uint8_t timer) static void turnOffPWM(uint8_t timer) { switch (timer) 3b0: 83 30 cpi r24, 0x03 ; 3 3b2: 91 f0 breq .+36 ; 0x3d8 <_Z4ISR0v+0x44> 3b4: 38 f4 brcc .+14 ; 0x3c4 <_Z4ISR0v+0x30> 3b6: 81 30 cpi r24, 0x01 ; 1 3b8: a9 f0 breq .+42 ; 0x3e4 <_Z4ISR0v+0x50> 3ba: 82 30 cpi r24, 0x02 ; 2 3bc: 01 f5 brne .+64 ; 0x3fe <_Z4ISR0v+0x6a> #if defined(TCCR0A) && defined(COM0A1) case TIMER0A: cbi(TCCR0A, COM0A1); break; #endif #if defined(TCCR0A) && defined(COM0B1) case TIMER0B: cbi(TCCR0A, COM0B1); break; 3be: 84 b5 in r24, 0x24 ; 36 3c0: 8f 7d andi r24, 0xDF ; 223 3c2: 12 c0 rjmp .+36 ; 0x3e8 <_Z4ISR0v+0x54> // //static inline void turnOffPWM(uint8_t timer) __attribute__ ((always_inline)); //static inline void turnOffPWM(uint8_t timer) static void turnOffPWM(uint8_t timer) { switch (timer) 3c4: 87 30 cpi r24, 0x07 ; 7 3c6: 91 f0 breq .+36 ; 0x3ec <_Z4ISR0v+0x58> 3c8: 88 30 cpi r24, 0x08 ; 8 3ca: a1 f0 breq .+40 ; 0x3f4 <_Z4ISR0v+0x60> 3cc: 84 30 cpi r24, 0x04 ; 4 3ce: b9 f4 brne .+46 ; 0x3fe <_Z4ISR0v+0x6a> { #if defined(TCCR1A) && defined(COM1A1) case TIMER1A: cbi(TCCR1A, COM1A1); break; #endif #if defined(TCCR1A) && defined(COM1B1) case TIMER1B: cbi(TCCR1A, COM1B1); break; 3d0: 80 91 80 00 lds r24, 0x0080 3d4: 8f 7d andi r24, 0xDF ; 223 3d6: 03 c0 rjmp .+6 ; 0x3de <_Z4ISR0v+0x4a> static void turnOffPWM(uint8_t timer) { switch (timer) { #if defined(TCCR1A) && defined(COM1A1) case TIMER1A: cbi(TCCR1A, COM1A1); break; 3d8: 80 91 80 00 lds r24, 0x0080 3dc: 8f 77 andi r24, 0x7F ; 127 #endif #if defined(TCCR1A) && defined(COM1B1) case TIMER1B: cbi(TCCR1A, COM1B1); break; 3de: 80 93 80 00 sts 0x0080, r24 3e2: 0d c0 rjmp .+26 ; 0x3fe <_Z4ISR0v+0x6a> #if defined(TCCR2) && defined(COM21) case TIMER2: cbi(TCCR2, COM21); break; #endif #if defined(TCCR0A) && defined(COM0A1) case TIMER0A: cbi(TCCR0A, COM0A1); break; 3e4: 84 b5 in r24, 0x24 ; 36 3e6: 8f 77 andi r24, 0x7F ; 127 #endif #if defined(TCCR0A) && defined(COM0B1) case TIMER0B: cbi(TCCR0A, COM0B1); break; 3e8: 84 bd out 0x24, r24 ; 36 3ea: 09 c0 rjmp .+18 ; 0x3fe <_Z4ISR0v+0x6a> #endif #if defined(TCCR2A) && defined(COM2A1) case TIMER2A: cbi(TCCR2A, COM2A1); break; 3ec: 80 91 b0 00 lds r24, 0x00B0 3f0: 8f 77 andi r24, 0x7F ; 127 3f2: 03 c0 rjmp .+6 ; 0x3fa <_Z4ISR0v+0x66> #endif #if defined(TCCR2A) && defined(COM2B1) case TIMER2B: cbi(TCCR2A, COM2B1); break; 3f4: 80 91 b0 00 lds r24, 0x00B0 3f8: 8f 7d andi r24, 0xDF ; 223 3fa: 80 93 b0 00 sts 0x00B0, r24 // If the pin that support PWM output, we need to turn it off // before getting a digital reading. if (timer != NOT_ON_TIMER) turnOffPWM(timer); if (*portInputRegister(port) & bit) return HIGH; 3fe: f0 e0 ldi r31, 0x00 ; 0 400: ee 0f add r30, r30 402: ff 1f adc r31, r31 404: e8 59 subi r30, 0x98 ; 152 406: ff 4f sbci r31, 0xFF ; 255 408: a5 91 lpm r26, Z+ 40a: b4 91 lpm r27, Z 40c: ec 91 ld r30, X 40e: e9 23 and r30, r25 410: 71 f0 breq .+28 ; 0x42e <__LOCK_REGION_LENGTH__+0x2e> }//end loop void ISR0(){ if(digitalRead(pingPin)==HIGH) { starttime=micros(); 412: 0e 94 96 01 call 0x32c ; 0x32c 416: 60 93 1e 01 sts 0x011E, r22 41a: 70 93 1f 01 sts 0x011F, r23 41e: 80 93 20 01 sts 0x0120, r24 422: 90 93 21 01 sts 0x0121, r25 attachInterrupt(digitalPinToInterrupt(pingPin), ISR0, FALLING); 426: 82 e0 ldi r24, 0x02 ; 2 428: 90 e0 ldi r25, 0x00 ; 0 42a: 0c 94 bc 01 jmp 0x378 ; 0x378 } else { endtime=micros(); 42e: 0e 94 96 01 call 0x32c ; 0x32c 432: 60 93 22 01 sts 0x0122, r22 436: 70 93 23 01 sts 0x0123, r23 43a: 80 93 24 01 sts 0x0124, r24 43e: 90 93 25 01 sts 0x0125, r25 attachInterrupt(digitalPinToInterrupt(pingPin), ISR0, RISING); 442: 83 e0 ldi r24, 0x03 ; 3 444: 90 e0 ldi r25, 0x00 ; 0 446: 0e 94 bc 01 call 0x378 ; 0x378 duration=endtime-starttime; 44a: 80 91 22 01 lds r24, 0x0122 44e: 90 91 23 01 lds r25, 0x0123 452: a0 91 24 01 lds r26, 0x0124 456: b0 91 25 01 lds r27, 0x0125 45a: 40 91 1e 01 lds r20, 0x011E 45e: 50 91 1f 01 lds r21, 0x011F 462: 60 91 20 01 lds r22, 0x0120 466: 70 91 21 01 lds r23, 0x0121 46a: 84 1b sub r24, r20 46c: 95 0b sbc r25, r21 46e: a6 0b sbc r26, r22 470: b7 0b sbc r27, r23 472: 80 93 2f 01 sts 0x012F, r24 476: 90 93 30 01 sts 0x0130, r25 47a: a0 93 31 01 sts 0x0131, r26 47e: b0 93 32 01 sts 0x0132, r27 newVal=true; 482: 81 e0 ldi r24, 0x01 ; 1 484: 80 93 33 01 sts 0x0133, r24 488: 08 95 ret 0000048a <_ZN5Print5writeEPKc.constprop.13>: int getWriteError() { return write_error; } void clearWriteError() { setWriteError(0); } virtual size_t write(uint8_t) = 0; size_t write(const char *str) { if (str == NULL) return 0; 48a: 00 97 sbiw r24, 0x00 ; 0 48c: 69 f0 breq .+26 ; 0x4a8 <_ZN5Print5writeEPKc.constprop.13+0x1e> return write((const uint8_t *)str, strlen(str)); 48e: fc 01 movw r30, r24 490: 01 90 ld r0, Z+ 492: 00 20 and r0, r0 494: e9 f7 brne .-6 ; 0x490 <_ZN5Print5writeEPKc.constprop.13+0x6> 496: 31 97 sbiw r30, 0x01 ; 1 498: af 01 movw r20, r30 49a: 48 1b sub r20, r24 49c: 59 0b sbc r21, r25 49e: bc 01 movw r22, r24 4a0: 84 e3 ldi r24, 0x34 ; 52 4a2: 91 e0 ldi r25, 0x01 ; 1 4a4: 0c 94 8c 00 jmp 0x118 ; 0x118 <_ZN5Print5writeEPKhj> } 4a8: 80 e0 ldi r24, 0x00 ; 0 4aa: 90 e0 ldi r25, 0x00 ; 0 4ac: 08 95 ret 000004ae <__cxa_pure_virtual>: extern "C" void __cxa_deleted_virtual(void) __attribute__ ((__noreturn__)); void __cxa_pure_virtual(void) { // We might want to write some diagnostics to uart in this case //std::terminate(); abort(); 4ae: 0e 94 ca 04 call 0x994 ; 0x994 000004b2 <__vector_19>: #elif defined(USART_UDRE_vect) ISR(USART_UDRE_vect) #else #error "Don't know what the Data Register Empty vector is called for Serial" #endif { 4b2: 1f 92 push r1 4b4: 0f 92 push r0 4b6: 0f b6 in r0, 0x3f ; 63 4b8: 0f 92 push r0 4ba: 11 24 eor r1, r1 4bc: 2f 93 push r18 4be: 3f 93 push r19 4c0: 4f 93 push r20 4c2: 5f 93 push r21 4c4: 6f 93 push r22 4c6: 7f 93 push r23 4c8: 8f 93 push r24 4ca: 9f 93 push r25 4cc: af 93 push r26 4ce: bf 93 push r27 4d0: ef 93 push r30 4d2: ff 93 push r31 Serial._tx_udr_empty_irq(); 4d4: 84 e3 ldi r24, 0x34 ; 52 4d6: 91 e0 ldi r25, 0x01 ; 1 4d8: 0e 94 02 01 call 0x204 ; 0x204 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> } 4dc: ff 91 pop r31 4de: ef 91 pop r30 4e0: bf 91 pop r27 4e2: af 91 pop r26 4e4: 9f 91 pop r25 4e6: 8f 91 pop r24 4e8: 7f 91 pop r23 4ea: 6f 91 pop r22 4ec: 5f 91 pop r21 4ee: 4f 91 pop r20 4f0: 3f 91 pop r19 4f2: 2f 91 pop r18 4f4: 0f 90 pop r0 4f6: 0f be out 0x3f, r0 ; 63 4f8: 0f 90 pop r0 4fa: 1f 90 pop r1 4fc: 18 95 reti 000004fe <__vector_18>: #elif defined(USART_RXC_vect) ISR(USART_RXC_vect) // ATmega8 #else #error "Don't know what the Data Received vector is called for Serial" #endif { 4fe: 1f 92 push r1 500: 0f 92 push r0 502: 0f b6 in r0, 0x3f ; 63 504: 0f 92 push r0 506: 11 24 eor r1, r1 508: 2f 93 push r18 50a: 8f 93 push r24 50c: 9f 93 push r25 50e: ef 93 push r30 510: ff 93 push r31 // Actual interrupt handlers ////////////////////////////////////////////////////////////// void HardwareSerial::_rx_complete_irq(void) { if (bit_is_clear(*_ucsra, UPE0)) { 512: e0 91 44 01 lds r30, 0x0144 516: f0 91 45 01 lds r31, 0x0145 51a: 80 81 ld r24, Z 51c: e0 91 4a 01 lds r30, 0x014A 520: f0 91 4b 01 lds r31, 0x014B 524: 82 fd sbrc r24, 2 526: 12 c0 rjmp .+36 ; 0x54c <__vector_18+0x4e> // No Parity error, read byte and store it in the buffer if there is // room unsigned char c = *_udr; 528: 90 81 ld r25, Z rx_buffer_index_t i = (unsigned int)(_rx_buffer_head + 1) % SERIAL_RX_BUFFER_SIZE; 52a: 80 91 4d 01 lds r24, 0x014D 52e: 8f 5f subi r24, 0xFF ; 255 530: 8f 73 andi r24, 0x3F ; 63 // if we should be storing the received character into the location // just before the tail (meaning that the head would advance to the // current location of the tail), we're about to overflow the buffer // and so we don't write the character or advance the head. if (i != _rx_buffer_tail) { 532: 20 91 4e 01 lds r18, 0x014E 536: 82 17 cp r24, r18 538: 51 f0 breq .+20 ; 0x54e <__vector_18+0x50> _rx_buffer[_rx_buffer_head] = c; 53a: e0 91 4d 01 lds r30, 0x014D 53e: f0 e0 ldi r31, 0x00 ; 0 540: ec 5c subi r30, 0xCC ; 204 542: fe 4f sbci r31, 0xFE ; 254 544: 95 8f std Z+29, r25 ; 0x1d _rx_buffer_head = i; 546: 80 93 4d 01 sts 0x014D, r24 54a: 01 c0 rjmp .+2 ; 0x54e <__vector_18+0x50> } } else { // Parity error, read byte but discard it *_udr; 54c: 80 81 ld r24, Z Serial._rx_complete_irq(); } 54e: ff 91 pop r31 550: ef 91 pop r30 552: 9f 91 pop r25 554: 8f 91 pop r24 556: 2f 91 pop r18 558: 0f 90 pop r0 55a: 0f be out 0x3f, r0 ; 63 55c: 0f 90 pop r0 55e: 1f 90 pop r1 560: 18 95 reti 00000562 <__vector_16>: #if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) ISR(TIM0_OVF_vect) #else ISR(TIMER0_OVF_vect) #endif { 562: 1f 92 push r1 564: 0f 92 push r0 566: 0f b6 in r0, 0x3f ; 63 568: 0f 92 push r0 56a: 11 24 eor r1, r1 56c: 2f 93 push r18 56e: 3f 93 push r19 570: 8f 93 push r24 572: 9f 93 push r25 574: af 93 push r26 576: bf 93 push r27 // copy these to local variables so they can be stored in registers // (volatile variables must be read from memory on every access) unsigned long m = timer0_millis; 578: 80 91 27 01 lds r24, 0x0127 57c: 90 91 28 01 lds r25, 0x0128 580: a0 91 29 01 lds r26, 0x0129 584: b0 91 2a 01 lds r27, 0x012A unsigned char f = timer0_fract; 588: 30 91 26 01 lds r19, 0x0126 m += MILLIS_INC; f += FRACT_INC; 58c: 23 e0 ldi r18, 0x03 ; 3 58e: 23 0f add r18, r19 if (f >= FRACT_MAX) { 590: 2d 37 cpi r18, 0x7D ; 125 592: 20 f4 brcc .+8 ; 0x59c <__vector_16+0x3a> // copy these to local variables so they can be stored in registers // (volatile variables must be read from memory on every access) unsigned long m = timer0_millis; unsigned char f = timer0_fract; m += MILLIS_INC; 594: 01 96 adiw r24, 0x01 ; 1 596: a1 1d adc r26, r1 598: b1 1d adc r27, r1 59a: 05 c0 rjmp .+10 ; 0x5a6 <__vector_16+0x44> f += FRACT_INC; if (f >= FRACT_MAX) { f -= FRACT_MAX; 59c: 26 e8 ldi r18, 0x86 ; 134 59e: 23 0f add r18, r19 m += 1; 5a0: 02 96 adiw r24, 0x02 ; 2 5a2: a1 1d adc r26, r1 5a4: b1 1d adc r27, r1 } timer0_fract = f; 5a6: 20 93 26 01 sts 0x0126, r18 timer0_millis = m; 5aa: 80 93 27 01 sts 0x0127, r24 5ae: 90 93 28 01 sts 0x0128, r25 5b2: a0 93 29 01 sts 0x0129, r26 5b6: b0 93 2a 01 sts 0x012A, r27 timer0_overflow_count++; 5ba: 80 91 2b 01 lds r24, 0x012B 5be: 90 91 2c 01 lds r25, 0x012C 5c2: a0 91 2d 01 lds r26, 0x012D 5c6: b0 91 2e 01 lds r27, 0x012E 5ca: 01 96 adiw r24, 0x01 ; 1 5cc: a1 1d adc r26, r1 5ce: b1 1d adc r27, r1 5d0: 80 93 2b 01 sts 0x012B, r24 5d4: 90 93 2c 01 sts 0x012C, r25 5d8: a0 93 2d 01 sts 0x012D, r26 5dc: b0 93 2e 01 sts 0x012E, r27 } 5e0: bf 91 pop r27 5e2: af 91 pop r26 5e4: 9f 91 pop r25 5e6: 8f 91 pop r24 5e8: 3f 91 pop r19 5ea: 2f 91 pop r18 5ec: 0f 90 pop r0 5ee: 0f be out 0x3f, r0 ; 63 5f0: 0f 90 pop r0 5f2: 1f 90 pop r1 5f4: 18 95 reti 000005f6 <__vector_2>: IMPLEMENT_ISR(INT7_vect, EXTERNAL_INT_7) #else IMPLEMENT_ISR(INT0_vect, EXTERNAL_INT_0) IMPLEMENT_ISR(INT1_vect, EXTERNAL_INT_1) 5f6: 1f 92 push r1 5f8: 0f 92 push r0 5fa: 0f b6 in r0, 0x3f ; 63 5fc: 0f 92 push r0 5fe: 11 24 eor r1, r1 600: 2f 93 push r18 602: 3f 93 push r19 604: 4f 93 push r20 606: 5f 93 push r21 608: 6f 93 push r22 60a: 7f 93 push r23 60c: 8f 93 push r24 60e: 9f 93 push r25 610: af 93 push r26 612: bf 93 push r27 614: ef 93 push r30 616: ff 93 push r31 618: e0 91 02 01 lds r30, 0x0102 61c: f0 91 03 01 lds r31, 0x0103 620: 09 95 icall 622: ff 91 pop r31 624: ef 91 pop r30 626: bf 91 pop r27 628: af 91 pop r26 62a: 9f 91 pop r25 62c: 8f 91 pop r24 62e: 7f 91 pop r23 630: 6f 91 pop r22 632: 5f 91 pop r21 634: 4f 91 pop r20 636: 3f 91 pop r19 638: 2f 91 pop r18 63a: 0f 90 pop r0 63c: 0f be out 0x3f, r0 ; 63 63e: 0f 90 pop r0 640: 1f 90 pop r1 642: 18 95 reti 00000644 <__vector_1>: IMPLEMENT_ISR(INT6_vect, EXTERNAL_INT_6) IMPLEMENT_ISR(INT7_vect, EXTERNAL_INT_7) #else IMPLEMENT_ISR(INT0_vect, EXTERNAL_INT_0) 644: 1f 92 push r1 646: 0f 92 push r0 648: 0f b6 in r0, 0x3f ; 63 64a: 0f 92 push r0 64c: 11 24 eor r1, r1 64e: 2f 93 push r18 650: 3f 93 push r19 652: 4f 93 push r20 654: 5f 93 push r21 656: 6f 93 push r22 658: 7f 93 push r23 65a: 8f 93 push r24 65c: 9f 93 push r25 65e: af 93 push r26 660: bf 93 push r27 662: ef 93 push r30 664: ff 93 push r31 666: e0 91 00 01 lds r30, 0x0100 66a: f0 91 01 01 lds r31, 0x0101 66e: 09 95 icall 670: ff 91 pop r31 672: ef 91 pop r30 674: bf 91 pop r27 676: af 91 pop r26 678: 9f 91 pop r25 67a: 8f 91 pop r24 67c: 7f 91 pop r23 67e: 6f 91 pop r22 680: 5f 91 pop r21 682: 4f 91 pop r20 684: 3f 91 pop r19 686: 2f 91 pop r18 688: 0f 90 pop r0 68a: 0f be out 0x3f, r0 ; 63 68c: 0f 90 pop r0 68e: 1f 90 pop r1 690: 18 95 reti 00000692
: void setupUSB() __attribute__((weak)); void setupUSB() { } int main(void) { 692: cf 93 push r28 694: df 93 push r29 696: cd b7 in r28, 0x3d ; 61 698: de b7 in r29, 0x3e ; 62 69a: a1 97 sbiw r28, 0x21 ; 33 69c: 0f b6 in r0, 0x3f ; 63 69e: f8 94 cli 6a0: de bf out 0x3e, r29 ; 62 6a2: 0f be out 0x3f, r0 ; 63 6a4: cd bf out 0x3d, r28 ; 61 void init() { // this needs to be called before setup() or some functions won't // work there sei(); 6a6: 78 94 sei // on the ATmega168, timer 0 is also used for fast hardware pwm // (using phase-correct PWM would mean that timer 0 overflowed half as often // resulting in different millis() behavior on the ATmega8 and ATmega168) #if defined(TCCR0A) && defined(WGM01) sbi(TCCR0A, WGM01); 6a8: 84 b5 in r24, 0x24 ; 36 6aa: 82 60 ori r24, 0x02 ; 2 6ac: 84 bd out 0x24, r24 ; 36 sbi(TCCR0A, WGM00); 6ae: 84 b5 in r24, 0x24 ; 36 6b0: 81 60 ori r24, 0x01 ; 1 6b2: 84 bd out 0x24, r24 ; 36 // this combination is for the standard atmega8 sbi(TCCR0, CS01); sbi(TCCR0, CS00); #elif defined(TCCR0B) && defined(CS01) && defined(CS00) // this combination is for the standard 168/328/1280/2560 sbi(TCCR0B, CS01); 6b4: 85 b5 in r24, 0x25 ; 37 6b6: 82 60 ori r24, 0x02 ; 2 6b8: 85 bd out 0x25, r24 ; 37 sbi(TCCR0B, CS00); 6ba: 85 b5 in r24, 0x25 ; 37 6bc: 81 60 ori r24, 0x01 ; 1 6be: 85 bd out 0x25, r24 ; 37 // enable timer 0 overflow interrupt #if defined(TIMSK) && defined(TOIE0) sbi(TIMSK, TOIE0); #elif defined(TIMSK0) && defined(TOIE0) sbi(TIMSK0, TOIE0); 6c0: 80 91 6e 00 lds r24, 0x006E 6c4: 81 60 ori r24, 0x01 ; 1 6c6: 80 93 6e 00 sts 0x006E, r24 // this is better for motors as it ensures an even waveform // note, however, that fast pwm mode can achieve a frequency of up // 8 MHz (with a 16 MHz clock) at 50% duty cycle #if defined(TCCR1B) && defined(CS11) && defined(CS10) TCCR1B = 0; 6ca: 10 92 81 00 sts 0x0081, r1 // set timer 1 prescale factor to 64 sbi(TCCR1B, CS11); 6ce: 80 91 81 00 lds r24, 0x0081 6d2: 82 60 ori r24, 0x02 ; 2 6d4: 80 93 81 00 sts 0x0081, r24 #if F_CPU >= 8000000L sbi(TCCR1B, CS10); 6d8: 80 91 81 00 lds r24, 0x0081 6dc: 81 60 ori r24, 0x01 ; 1 6de: 80 93 81 00 sts 0x0081, r24 sbi(TCCR1, CS10); #endif #endif // put timer 1 in 8-bit phase correct pwm mode #if defined(TCCR1A) && defined(WGM10) sbi(TCCR1A, WGM10); 6e2: 80 91 80 00 lds r24, 0x0080 6e6: 81 60 ori r24, 0x01 ; 1 6e8: 80 93 80 00 sts 0x0080, r24 // set timer 2 prescale factor to 64 #if defined(TCCR2) && defined(CS22) sbi(TCCR2, CS22); #elif defined(TCCR2B) && defined(CS22) sbi(TCCR2B, CS22); 6ec: 80 91 b1 00 lds r24, 0x00B1 6f0: 84 60 ori r24, 0x04 ; 4 6f2: 80 93 b1 00 sts 0x00B1, r24 // configure timer 2 for phase correct pwm (8-bit) #if defined(TCCR2) && defined(WGM20) sbi(TCCR2, WGM20); #elif defined(TCCR2A) && defined(WGM20) sbi(TCCR2A, WGM20); 6f6: 80 91 b0 00 lds r24, 0x00B0 6fa: 81 60 ori r24, 0x01 ; 1 6fc: 80 93 b0 00 sts 0x00B0, r24 #endif #if defined(ADCSRA) // set a2d prescaler so we are inside the desired 50-200 KHz range. #if F_CPU >= 16000000 // 16 MHz / 128 = 125 KHz sbi(ADCSRA, ADPS2); 700: 80 91 7a 00 lds r24, 0x007A 704: 84 60 ori r24, 0x04 ; 4 706: 80 93 7a 00 sts 0x007A, r24 sbi(ADCSRA, ADPS1); 70a: 80 91 7a 00 lds r24, 0x007A 70e: 82 60 ori r24, 0x02 ; 2 710: 80 93 7a 00 sts 0x007A, r24 sbi(ADCSRA, ADPS0); 714: 80 91 7a 00 lds r24, 0x007A 718: 81 60 ori r24, 0x01 ; 1 71a: 80 93 7a 00 sts 0x007A, r24 cbi(ADCSRA, ADPS2); cbi(ADCSRA, ADPS1); sbi(ADCSRA, ADPS0); #endif // enable a2d conversions sbi(ADCSRA, ADEN); 71e: 80 91 7a 00 lds r24, 0x007A 722: 80 68 ori r24, 0x80 ; 128 724: 80 93 7a 00 sts 0x007A, r24 // here so they can be used as normal digital i/o; they will be // reconnected in Serial.begin() #if defined(UCSRB) UCSRB = 0; #elif defined(UCSR0B) UCSR0B = 0; 728: 10 92 c1 00 sts 0x00C1, r1 #include "wiring_private.h" #include "pins_arduino.h" void pinMode(uint8_t pin, uint8_t mode) { uint8_t bit = digitalPinToBitMask(pin); 72c: e0 eb ldi r30, 0xB0 ; 176 72e: f0 e0 ldi r31, 0x00 ; 0 730: 24 91 lpm r18, Z uint8_t port = digitalPinToPort(pin); 732: ec e9 ldi r30, 0x9C ; 156 734: f0 e0 ldi r31, 0x00 ; 0 736: 84 91 lpm r24, Z volatile uint8_t *reg, *out; if (port == NOT_A_PIN) return; 738: 88 23 and r24, r24 73a: c9 f0 breq .+50 ; 0x76e // JWS: can I let the optimizer do this? reg = portModeRegister(port); 73c: 90 e0 ldi r25, 0x00 ; 0 73e: 88 0f add r24, r24 740: 99 1f adc r25, r25 742: fc 01 movw r30, r24 744: e0 57 subi r30, 0x70 ; 112 746: ff 4f sbci r31, 0xFF ; 255 748: 45 91 lpm r20, Z+ 74a: 54 91 lpm r21, Z out = portOutputRegister(port); 74c: fc 01 movw r30, r24 74e: ea 57 subi r30, 0x7A ; 122 750: ff 4f sbci r31, 0xFF ; 255 752: a5 91 lpm r26, Z+ 754: b4 91 lpm r27, Z if (mode == INPUT) { uint8_t oldSREG = SREG; 756: 9f b7 in r25, 0x3f ; 63 cli(); 758: f8 94 cli *reg &= ~bit; 75a: fa 01 movw r30, r20 75c: 80 81 ld r24, Z 75e: 20 95 com r18 760: 82 23 and r24, r18 762: 80 83 st Z, r24 *out &= ~bit; 764: 8c 91 ld r24, X 766: e2 2f mov r30, r18 768: e8 23 and r30, r24 76a: ec 93 st X, r30 SREG = oldSREG; 76c: 9f bf out 0x3f, r25 ; 63 void HardwareSerial::begin(unsigned long baud, byte config) { // Try u2x mode first uint16_t baud_setting = (F_CPU / 4 / baud - 1) / 2; *_ucsra = 1 << U2X0; 76e: e0 91 44 01 lds r30, 0x0144 772: f0 91 45 01 lds r31, 0x0145 776: 82 e0 ldi r24, 0x02 ; 2 778: 80 83 st Z, r24 *_ucsra = 0; baud_setting = (F_CPU / 8 / baud - 1) / 2; } // assign the baud_setting, a.k.a. ubrr (USART Baud Rate Register) *_ubrrh = baud_setting >> 8; 77a: e0 91 40 01 lds r30, 0x0140 77e: f0 91 41 01 lds r31, 0x0141 782: 10 82 st Z, r1 *_ubrrl = baud_setting; 784: e0 91 42 01 lds r30, 0x0142 788: f0 91 43 01 lds r31, 0x0143 78c: 8f ec ldi r24, 0xCF ; 207 78e: 80 83 st Z, r24 _written = false; 790: 10 92 4c 01 sts 0x014C, r1 //set the data bits, parity, and stop bits #if defined(__AVR_ATmega8__) config |= 0x80; // select UCSRC register (shared with UBRRH) #endif *_ucsrc = config; 794: e0 91 48 01 lds r30, 0x0148 798: f0 91 49 01 lds r31, 0x0149 79c: 86 e0 ldi r24, 0x06 ; 6 79e: 80 83 st Z, r24 sbi(*_ucsrb, RXEN0); 7a0: e0 91 46 01 lds r30, 0x0146 7a4: f0 91 47 01 lds r31, 0x0147 7a8: 80 81 ld r24, Z 7aa: 80 61 ori r24, 0x10 ; 16 7ac: 80 83 st Z, r24 sbi(*_ucsrb, TXEN0); 7ae: e0 91 46 01 lds r30, 0x0146 7b2: f0 91 47 01 lds r31, 0x0147 7b6: 80 81 ld r24, Z 7b8: 88 60 ori r24, 0x08 ; 8 7ba: 80 83 st Z, r24 sbi(*_ucsrb, RXCIE0); 7bc: e0 91 46 01 lds r30, 0x0146 7c0: f0 91 47 01 lds r31, 0x0147 7c4: 80 81 ld r24, Z 7c6: 80 68 ori r24, 0x80 ; 128 7c8: 80 83 st Z, r24 cbi(*_ucsrb, UDRIE0); 7ca: e0 91 46 01 lds r30, 0x0146 7ce: f0 91 47 01 lds r31, 0x0147 7d2: 80 81 ld r24, Z 7d4: 8f 7d andi r24, 0xDF ; 223 7d6: 80 83 st Z, r24 void setup() { pinMode(pingPin, INPUT); // initialize serial communication: Serial.begin(9600); attachInterrupt(digitalPinToInterrupt(pingPin), ISR0, RISING); 7d8: 83 e0 ldi r24, 0x03 ; 3 7da: 90 e0 ldi r25, 0x00 ; 0 7dc: 0e 94 bc 01 call 0x378 ; 0x378 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; 7e0: 9a e0 ldi r25, 0x0A ; 10 7e2: 89 2e mov r8, r25 7e4: 91 2c mov r9, r1 7e6: a1 2c mov r10, r1 7e8: b1 2c mov r11, r1 } void loop() { if (newVal) { 7ea: 80 91 33 01 lds r24, 0x0133 7ee: 88 23 and r24, r24 7f0: 09 f4 brne .+2 ; 0x7f4 7f2: 78 c0 rjmp .+240 ; 0x8e4 Serial.print(duration); 7f4: c0 90 2f 01 lds r12, 0x012F 7f8: d0 90 30 01 lds r13, 0x0130 7fc: e0 90 31 01 lds r14, 0x0131 800: f0 90 32 01 lds r15, 0x0132 size_t Print::print(long n, int base) { if (base == 0) { return write(n); } else if (base == 10) { if (n < 0) { 804: f7 fe sbrs r15, 7 806: 26 c0 rjmp .+76 ; 0x854 return write(str); } size_t Print::print(char c) { return write(c); 808: e0 91 34 01 lds r30, 0x0134 80c: f0 91 35 01 lds r31, 0x0135 810: 01 90 ld r0, Z+ 812: f0 81 ld r31, Z 814: e0 2d mov r30, r0 816: 6d e2 ldi r22, 0x2D ; 45 818: 84 e3 ldi r24, 0x34 ; 52 81a: 91 e0 ldi r25, 0x01 ; 1 81c: 09 95 icall if (base == 0) { return write(n); } else if (base == 10) { if (n < 0) { int t = print('-'); n = -n; 81e: 22 27 eor r18, r18 820: 33 27 eor r19, r19 822: a9 01 movw r20, r18 824: 2c 19 sub r18, r12 826: 3d 09 sbc r19, r13 828: 4e 09 sbc r20, r14 82a: 5f 09 sbc r21, r15 size_t Print::printNumber(unsigned long n, uint8_t base) { char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. char *str = &buf[sizeof(buf) - 1]; *str = '\0'; 82c: 19 a2 std Y+33, r1 ; 0x21 82e: 8e 01 movw r16, r28 830: 0f 5d subi r16, 0xDF ; 223 832: 1f 4f sbci r17, 0xFF ; 255 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; n /= base; 834: ca 01 movw r24, r20 836: b9 01 movw r22, r18 838: a5 01 movw r20, r10 83a: 94 01 movw r18, r8 83c: 0e 94 a2 04 call 0x944 ; 0x944 <__udivmodsi4> *--str = c < 10 ? c + '0' : c + 'A' - 10; 840: 60 5d subi r22, 0xD0 ; 208 842: f8 01 movw r30, r16 844: 62 93 st -Z, r22 846: 8f 01 movw r16, r30 *str = '\0'; // prevent crash if called with base == 1 if (base < 2) base = 10; do { 848: 21 15 cp r18, r1 84a: 31 05 cpc r19, r1 84c: 41 05 cpc r20, r1 84e: 51 05 cpc r21, r1 850: 89 f7 brne .-30 ; 0x834 852: 15 c0 rjmp .+42 ; 0x87e if (n < 0) { int t = print('-'); n = -n; return printNumber(n, 10) + t; } return printNumber(n, 10); 854: a7 01 movw r20, r14 856: 96 01 movw r18, r12 size_t Print::printNumber(unsigned long n, uint8_t base) { char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. char *str = &buf[sizeof(buf) - 1]; *str = '\0'; 858: 19 a2 std Y+33, r1 ; 0x21 85a: 8e 01 movw r16, r28 85c: 0f 5d subi r16, 0xDF ; 223 85e: 1f 4f sbci r17, 0xFF ; 255 // prevent crash if called with base == 1 if (base < 2) base = 10; do { char c = n % base; n /= base; 860: ca 01 movw r24, r20 862: b9 01 movw r22, r18 864: a5 01 movw r20, r10 866: 94 01 movw r18, r8 868: 0e 94 a2 04 call 0x944 ; 0x944 <__udivmodsi4> *--str = c < 10 ? c + '0' : c + 'A' - 10; 86c: 60 5d subi r22, 0xD0 ; 208 86e: f8 01 movw r30, r16 870: 62 93 st -Z, r22 872: 8f 01 movw r16, r30 *str = '\0'; // prevent crash if called with base == 1 if (base < 2) base = 10; do { 874: 21 15 cp r18, r1 876: 31 05 cpc r19, r1 878: 41 05 cpc r20, r1 87a: 51 05 cpc r21, r1 87c: 89 f7 brne .-30 ; 0x860 n /= base; *--str = c < 10 ? c + '0' : c + 'A' - 10; } while(n); return write(str); 87e: c8 01 movw r24, r16 880: 0e 94 45 02 call 0x48a ; 0x48a <_ZN5Print5writeEPKc.constprop.13> return write(s.c_str(), s.length()); } size_t Print::print(const char str[]) { return write(str); 884: 86 e1 ldi r24, 0x16 ; 22 886: 91 e0 ldi r25, 0x01 ; 1 888: 0e 94 45 02 call 0x48a ; 0x48a <_ZN5Print5writeEPKc.constprop.13> return x.printTo(*this); } size_t Print::println(void) { return write("\r\n"); 88c: 8a e1 ldi r24, 0x1A ; 26 88e: 91 e0 ldi r25, 0x01 ; 1 890: 0e 94 45 02 call 0x48a ; 0x48a <_ZN5Print5writeEPKc.constprop.13> Serial.print("us "); Serial.println(); newVal=false; 894: 10 92 33 01 sts 0x0133, r1 return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond()); } void delay(unsigned long ms) { uint32_t start = micros(); 898: 0e 94 96 01 call 0x32c ; 0x32c 89c: 2b 01 movw r4, r22 89e: 3c 01 movw r6, r24 8a0: 84 e6 ldi r24, 0x64 ; 100 8a2: c8 2e mov r12, r24 8a4: d1 2c mov r13, r1 8a6: e1 2c mov r14, r1 8a8: f1 2c mov r15, r1 while (ms > 0) { yield(); while ( ms > 0 && (micros() - start) >= 1000) { 8aa: 0e 94 96 01 call 0x32c ; 0x32c 8ae: dc 01 movw r26, r24 8b0: cb 01 movw r24, r22 8b2: 84 19 sub r24, r4 8b4: 95 09 sbc r25, r5 8b6: a6 09 sbc r26, r6 8b8: b7 09 sbc r27, r7 8ba: 88 3e cpi r24, 0xE8 ; 232 8bc: 93 40 sbci r25, 0x03 ; 3 8be: a1 05 cpc r26, r1 8c0: b1 05 cpc r27, r1 8c2: 58 f0 brcs .+22 ; 0x8da ms--; 8c4: f1 e0 ldi r31, 0x01 ; 1 8c6: cf 1a sub r12, r31 8c8: d1 08 sbc r13, r1 8ca: e1 08 sbc r14, r1 8cc: f1 08 sbc r15, r1 start += 1000; 8ce: 28 ee ldi r18, 0xE8 ; 232 8d0: 42 0e add r4, r18 8d2: 23 e0 ldi r18, 0x03 ; 3 8d4: 52 1e adc r5, r18 8d6: 61 1c adc r6, r1 8d8: 71 1c adc r7, r1 { uint32_t start = micros(); while (ms > 0) { yield(); while ( ms > 0 && (micros() - start) >= 1000) { 8da: c1 14 cp r12, r1 8dc: d1 04 cpc r13, r1 8de: e1 04 cpc r14, r1 8e0: f1 04 cpc r15, r1 8e2: 19 f7 brne .-58 ; 0x8aa setup(); for (;;) { loop(); if (serialEventRun) serialEventRun(); 8e4: 0e 94 8c 01 call 0x318 ; 0x318 <_Z14serialEventRunv> 8e8: 80 cf rjmp .-256 ; 0x7ea 000008ea <_GLOBAL__sub_I___vector_18>: size_t printNumber(unsigned long, uint8_t); size_t printFloat(double, uint8_t); protected: void setWriteError(int err = 1) { write_error = err; } public: Print() : write_error(0) {} 8ea: e4 e3 ldi r30, 0x34 ; 52 8ec: f1 e0 ldi r31, 0x01 ; 1 8ee: 13 82 std Z+3, r1 ; 0x03 8f0: 12 82 std Z+2, r1 ; 0x02 public: virtual int available() = 0; virtual int read() = 0; virtual int peek() = 0; Stream() {_timeout=1000;} 8f2: 88 ee ldi r24, 0xE8 ; 232 8f4: 93 e0 ldi r25, 0x03 ; 3 8f6: a0 e0 ldi r26, 0x00 ; 0 8f8: b0 e0 ldi r27, 0x00 ; 0 8fa: 84 83 std Z+4, r24 ; 0x04 8fc: 95 83 std Z+5, r25 ; 0x05 8fe: a6 83 std Z+6, r26 ; 0x06 900: b7 83 std Z+7, r27 ; 0x07 volatile uint8_t *ucsrc, volatile uint8_t *udr) : _ubrrh(ubrrh), _ubrrl(ubrrl), _ucsra(ucsra), _ucsrb(ucsrb), _ucsrc(ucsrc), _udr(udr), _rx_buffer_head(0), _rx_buffer_tail(0), _tx_buffer_head(0), _tx_buffer_tail(0) 902: 88 e0 ldi r24, 0x08 ; 8 904: 91 e0 ldi r25, 0x01 ; 1 906: 91 83 std Z+1, r25 ; 0x01 908: 80 83 st Z, r24 90a: 85 ec ldi r24, 0xC5 ; 197 90c: 90 e0 ldi r25, 0x00 ; 0 90e: 95 87 std Z+13, r25 ; 0x0d 910: 84 87 std Z+12, r24 ; 0x0c 912: 84 ec ldi r24, 0xC4 ; 196 914: 90 e0 ldi r25, 0x00 ; 0 916: 97 87 std Z+15, r25 ; 0x0f 918: 86 87 std Z+14, r24 ; 0x0e 91a: 80 ec ldi r24, 0xC0 ; 192 91c: 90 e0 ldi r25, 0x00 ; 0 91e: 91 8b std Z+17, r25 ; 0x11 920: 80 8b std Z+16, r24 ; 0x10 922: 81 ec ldi r24, 0xC1 ; 193 924: 90 e0 ldi r25, 0x00 ; 0 926: 93 8b std Z+19, r25 ; 0x13 928: 82 8b std Z+18, r24 ; 0x12 92a: 82 ec ldi r24, 0xC2 ; 194 92c: 90 e0 ldi r25, 0x00 ; 0 92e: 95 8b std Z+21, r25 ; 0x15 930: 84 8b std Z+20, r24 ; 0x14 932: 86 ec ldi r24, 0xC6 ; 198 934: 90 e0 ldi r25, 0x00 ; 0 936: 97 8b std Z+23, r25 ; 0x17 938: 86 8b std Z+22, r24 ; 0x16 93a: 11 8e std Z+25, r1 ; 0x19 93c: 12 8e std Z+26, r1 ; 0x1a 93e: 13 8e std Z+27, r1 ; 0x1b 940: 14 8e std Z+28, r1 ; 0x1c 942: 08 95 ret 00000944 <__udivmodsi4>: 944: a1 e2 ldi r26, 0x21 ; 33 946: 1a 2e mov r1, r26 948: aa 1b sub r26, r26 94a: bb 1b sub r27, r27 94c: fd 01 movw r30, r26 94e: 0d c0 rjmp .+26 ; 0x96a <__udivmodsi4_ep> 00000950 <__udivmodsi4_loop>: 950: aa 1f adc r26, r26 952: bb 1f adc r27, r27 954: ee 1f adc r30, r30 956: ff 1f adc r31, r31 958: a2 17 cp r26, r18 95a: b3 07 cpc r27, r19 95c: e4 07 cpc r30, r20 95e: f5 07 cpc r31, r21 960: 20 f0 brcs .+8 ; 0x96a <__udivmodsi4_ep> 962: a2 1b sub r26, r18 964: b3 0b sbc r27, r19 966: e4 0b sbc r30, r20 968: f5 0b sbc r31, r21 0000096a <__udivmodsi4_ep>: 96a: 66 1f adc r22, r22 96c: 77 1f adc r23, r23 96e: 88 1f adc r24, r24 970: 99 1f adc r25, r25 972: 1a 94 dec r1 974: 69 f7 brne .-38 ; 0x950 <__udivmodsi4_loop> 976: 60 95 com r22 978: 70 95 com r23 97a: 80 95 com r24 97c: 90 95 com r25 97e: 9b 01 movw r18, r22 980: ac 01 movw r20, r24 982: bd 01 movw r22, r26 984: cf 01 movw r24, r30 986: 08 95 ret 00000988 <__tablejump2__>: 988: ee 0f add r30, r30 98a: ff 1f adc r31, r31 98c: 05 90 lpm r0, Z+ 98e: f4 91 lpm r31, Z 990: e0 2d mov r30, r0 992: 09 94 ijmp 00000994 : 994: 81 e0 ldi r24, 0x01 ; 1 996: 90 e0 ldi r25, 0x00 ; 0 998: f8 94 cli 99a: 0c 94 cf 04 jmp 0x99e ; 0x99e <_exit> 0000099e <_exit>: 99e: f8 94 cli 000009a0 <__stop_program>: 9a0: ff cf rjmp .-2 ; 0x9a0 <__stop_program>